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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-02 00:34:44 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-02 00:34:44 +0000 |
commit | 091f2a0c4f25a3fc45bf63939266d5562c85e7cf (patch) | |
tree | 2b819f459fe3356983b56f2a26f5715301389158 /firmware/target/arm/as3525 | |
parent | 311ae23a540a0918a769bca6e3c53ad0d4556273 (diff) | |
download | rockbox-091f2a0c4f25a3fc45bf63939266d5562c85e7cf.tar.gz rockbox-091f2a0c4f25a3fc45bf63939266d5562c85e7cf.zip |
AS3525: disable interrupts, higher clock frequencies
fclk (CPU) at 240MHz
pclk (peripherals) at 64MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18972 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 45f36bda8c..a28ffc473e 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -201,7 +201,22 @@ void system_init(void) | |||
201 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; | 201 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; |
202 | #endif | 202 | #endif |
203 | 203 | ||
204 | CGU_PROC = 0; /* fclk 24 MHz */ | ||
205 | CGU_PERI &= ~0x7f; /* pclk 24 MHz */ | ||
206 | |||
204 | asm volatile( | 207 | asm volatile( |
208 | "mrc p15, 0, r0, c1, c0 \n" | ||
209 | "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */ | ||
210 | "mcr p15, 0, r0, c1, c0 \n" | ||
211 | : : : "r0" ); | ||
212 | |||
213 | CGU_PLLA = 0x4330; /* PLLA 384 MHz */ | ||
214 | CGU_PROC = (3<<2)|0x01; /* fclk = PLLA*5/8 = 240 MHz */ | ||
215 | |||
216 | asm volatile( | ||
217 | "mrs r0, cpsr \n" | ||
218 | "orr r0, r0, #0x80 \n" /* disable interrupts */ | ||
219 | "msr cpsr, r0 \n" | ||
205 | "mov r0, #0 \n" | 220 | "mov r0, #0 \n" |
206 | "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ | 221 | "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ |
207 | "mrc p15, 0, r0, c1, c0 \n" /* control register */ | 222 | "mrc p15, 0, r0, c1, c0 \n" /* control register */ |
@@ -210,8 +225,9 @@ void system_init(void) | |||
210 | "mcr p15, 0, r0, c1, c0 \n" | 225 | "mcr p15, 0, r0, c1, c0 \n" |
211 | : : : "r0" ); | 226 | : : : "r0" ); |
212 | 227 | ||
213 | |||
214 | sdram_init(); | 228 | sdram_init(); |
229 | |||
230 | CGU_PERI |= (5<<2)|0x01; /* pclk = PLLA / 6 = 64 MHz */ | ||
215 | } | 231 | } |
216 | 232 | ||
217 | void system_reboot(void) | 233 | void system_reboot(void) |