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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2010-06-18 04:55:55 +0000
committerTobias Diedrich <ranma+coreboot@tdiedrich.de>2010-06-18 04:55:55 +0000
commitfe47966f0e06c14fa0b82325c1eee029a0be827a (patch)
treeefd2aefb4a602f06fe16c744be3e891d239c6a79 /firmware/target/arm/as3525/usb-drv-as3525.c
parentd9c9fe305c01c30e4f9e8c981a7069ef8e94ca81 (diff)
downloadrockbox-fe47966f0e06c14fa0b82325c1eee029a0be827a.tar.gz
rockbox-fe47966f0e06c14fa0b82325c1eee029a0be827a.zip
Move usb-drv-as3525 defines into header file
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26907 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/usb-drv-as3525.c')
-rw-r--r--firmware/target/arm/as3525/usb-drv-as3525.c293
1 files changed, 2 insertions, 291 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525.c b/firmware/target/arm/as3525/usb-drv-as3525.c
index fe3b38fdb5..a5a3689403 100644
--- a/firmware/target/arm/as3525/usb-drv-as3525.c
+++ b/firmware/target/arm/as3525/usb-drv-as3525.c
@@ -7,7 +7,7 @@
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id$ 8 * $Id$
9 * 9 *
10 * Copyright © 2009 Rafaël Carré 10 * Copyright © 2010 Tobias Diedrich
11 * 11 *
12 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License 13 * modify it under the terms of the GNU General Public License
@@ -36,296 +36,7 @@
36 36
37#if defined(USE_ROCKBOX_USB) 37#if defined(USE_ROCKBOX_USB)
38 38
39#define USB_NUM_EPS 4 39#include "usb-drv-as3525.h"
40
41typedef struct {
42 volatile unsigned long offset[4096];
43} __regbase;
44
45/*
46 * This generates better code.
47 * Stripped object size with __regbase construct: 5192
48 * Stripped object size with *((volatile int)(x)): 5228
49 */
50#define USB_REG(x) ((__regbase *)(USB_BASE))->offset[(x)>>2]
51
52/* 4 input endpoints */
53#define USB_IEP_CTRL(i) USB_REG(0x0000 + i*0x20)
54#define USB_IEP_STS(i) USB_REG(0x0004 + i*0x20)
55/* txfsize: bits 0-15 */
56#define USB_IEP_TXFSIZE(i) USB_REG(0x0008 + i*0x20)
57/* mps: bits 0-10 (max 2047) */
58#define USB_IEP_MPS(i) USB_REG(0x000C + i*0x20)
59#define USB_IEP_DESC_PTR(i) USB_REG(0x0014 + i*0x20)
60#define USB_IEP_STS_MASK(i) USB_REG(0x0018 + i*0x20)
61
62/* 4 output endpoints */
63#define USB_OEP_CTRL(i) USB_REG(0x0200 + i*0x20)
64#define USB_OEP_STS(i) USB_REG(0x0204 + i*0x20)
65/* 'rx packet frame number' */
66#define USB_OEP_RXFR(i) USB_REG(0x0208 + i*0x20)
67/* mps: bits 0-10 (max 2047), bits 23-31 are fifo size */
68#define USB_OEP_MPS(i) USB_REG(0x020C + i*0x20)
69#define USB_OEP_SUP_PTR(i) USB_REG(0x0210 + i*0x20)
70#define USB_OEP_DESC_PTR(i) USB_REG(0x0214 + i*0x20)
71#define USB_OEP_STS_MASK(i) USB_REG(0x0218 + i*0x20)
72
73/* more general macro */
74/* d: true => IN, false => OUT */
75#define USB_EP_CTRL(i,d) USB_REG(0x0000 + i*0x20 + (!d)*0x0200)
76#define USB_EP_STS(i,d) USB_REG(0x0004 + i*0x20 + (!d)*0x0200)
77#define USB_EP_TXFSIZE(i,d) USB_REG(0x0008 + i*0x20 + (!d)*0x0200)
78#define USB_EP_MPS(i,d) USB_REG(0x000C + i*0x20 + (!d)*0x0200)
79#define USB_EP_DESC_PTR(i,d) USB_REG(0x0014 + i*0x20 + (!d)*0x0200)
80#define USB_EP_STS_MASK(i,d) USB_REG(0x0018 + i*0x20 + (!d)*0x0200)
81
82#define USB_DEV_CFG USB_REG(0x0400)
83#define USB_DEV_CTRL USB_REG(0x0404)
84#define USB_DEV_STS USB_REG(0x0408)
85#define USB_DEV_INTR USB_REG(0x040C)
86#define USB_DEV_INTR_MASK USB_REG(0x0410)
87#define USB_DEV_EP_INTR USB_REG(0x0414)
88#define USB_DEV_EP_INTR_MASK USB_REG(0x0418)
89
90/* NOTE: Not written to in OF, most lied in host mode? */
91#define USB_PHY_EP0_INFO USB_REG(0x0504)
92#define USB_PHY_EP1_INFO USB_REG(0x0508)
93#define USB_PHY_EP2_INFO USB_REG(0x050C)
94#define USB_PHY_EP3_INFO USB_REG(0x0510)
95#define USB_PHY_EP4_INFO USB_REG(0x0514)
96#define USB_PHY_EP5_INFO USB_REG(0x0518)
97
98/* 4 channels */
99#define USB_HOST_CH_SPLT(i) USB_REG(0x1000 + i*0x20)
100#define USB_HOST_CH_STS(i) USB_REG(0x1004 + i*0x20)
101#define USB_HOST_CH_TXFSIZE(i) USB_REG(0x1008 + i*0x20)
102#define USB_HOST_CH_REQ(i) USB_REG(0x100C + i*0x20)
103#define USB_HOST_CH_PER_INFO(i) USB_REG(0x1010 + i*0x20)
104#define USB_HOST_CH_DESC_PTR(i) USB_REG(0x1014 + i*0x20)
105#define USB_HOST_CH_STS_MASK(i) USB_REG(0x1018 + i*0x20)
106
107#define USB_HOST_CFG USB_REG(0x1400)
108#define USB_HOST_CTRL USB_REG(0x1404)
109#define USB_HOST_INTR USB_REG(0x140C)
110#define USB_HOST_INTR_MASK USB_REG(0x1410)
111#define USB_HOST_CH_INTR USB_REG(0x1414)
112#define USB_HOST_CH_INTR_MASK USB_REG(0x1418)
113#define USB_HOST_FRAME_INT USB_REG(0x141C)
114#define USB_HOST_FRAME_REM USB_REG(0x1420)
115#define USB_HOST_FRAME_NUM USB_REG(0x1424)
116
117#define USB_HOST_PORT0_CTRL_STS USB_REG(0x1500)
118
119#define USB_OTG_CSR USB_REG(0x2000)
120#define USB_I2C_CSR USB_REG(0x2004)
121#define USB_GPIO_CSR USB_REG(0x2008)
122#define USB_SNPSID_CSR USB_REG(0x200C)
123#define USB_USERID_CSR USB_REG(0x2010)
124#define USB_USER_CONF1 USB_REG(0x2014)
125#define USB_USER_CONF2 USB_REG(0x2018)
126#define USB_USER_CONF3 USB_REG(0x201C)
127#define USB_USER_CONF4 USB_REG(0x2020)
128/* USER_CONF5 seems to the same as USBt least on read */
129#define USB_USER_CONF5 USB_REG(0x2024)
130
131#define USB_CSR_NUM_MASK 0x0000000f
132#define USB_CSR_DIR_MASK 0x00000010
133#define USB_CSR_DIR_IN 0x00000010
134#define USB_CSR_DIR_OUT 0x00000000
135#define USB_CSR_TYPE_MASK 0x00000060
136#define USB_CSR_TYPE_CTL 0x00000000
137#define USB_CSR_TYPE_ISO 0x00000020
138#define USB_CSR_TYPE_BULK 0x00000040
139#define USB_CSR_TYPE_INT 0x00000060
140#define USB_CSR_CFG_MASK 0x00000780
141#define USB_CSR_INTF_MASK 0x00007800
142#define USB_CSR_ALT_MASK 0x00078000
143#define USB_CSR_MAXPKT_MASK 0x3ff80000
144#define USB_CSR_ISOMULT_MASK 0xc0000000
145
146/* write bits 31..16 */
147#define USB_GPIO_IDDIG_SEL (1<<30)
148#define USB_GPIO_FS_DATA_EXT (1<<29)
149#define USB_GPIO_FS_SE0_EXT (1<<28)
150#define USB_GPIO_FS_XCVR_OWNER (1<<27)
151#define USB_GPIO_TX_ENABLE_N (1<<26)
152#define USB_GPIO_TX_BIT_STUFF_EN (1<<25)
153#define USB_GPIO_BSESSVLD_EXT (1<<24)
154#define USB_GPIO_ASESSVLD_EXT (1<<23)
155#define USB_GPIO_VBUS_VLD_EXT (1<<22)
156#define USB_GPIO_VBUS_VLD_EXT_SEL (1<<21)
157#define USB_GPIO_XO_ON (1<<20)
158#define USB_GPIO_CLK_SEL11 (3<<18)
159#define USB_GPIO_CLK_SEL10 (2<<18)
160#define USB_GPIO_CLK_SEL01 (1<<18)
161#define USB_GPIO_CLK_SEL00 (0<<18)
162#define USB_GPIO_XO_EXT_CLK_ENBN (1<<17)
163#define USB_GPIO_XO_REFCLK_ENB (1<<16)
164/* readronly bits 15..0 */
165#define USB_GPIO_PHY_VBUSDRV (1<< 1)
166#define USB_GPIO_HS_INTR (1<< 0)
167
168/* Device Control Register and bit fields */
169#define USB_DEV_CTRL_REMOTE_WAKEUP 0x00000001 // set remote wake-up signal
170#define USB_DEV_CTRL_RESERVED0 0x00000002 // reserved, ro, read as 0
171#define USB_DEV_CTRL_RDE 0x00000004 // receive dma enable
172#define USB_DEV_CTRL_TDE 0x00000008 // transmit dma enable
173#define USB_DEV_CTRL_DESC_UPDATE 0x00000010 // update desc after dma
174#define USB_DEV_CTRL_BE 0x00000020 // big endian when set (ro)
175#define USB_DEV_CTRL_BUFFER_FULL 0x00000040
176#define USB_DEV_CTRL_THRES_ENABLE 0x00000080 // threshold enable
177#define USB_DEV_CTRL_BURST_ENABLE 0x00000100 // ahb burst enable
178#define USB_DEV_CTRL_MODE 0x00000200 // 0=slave, 1=dma
179#define USB_DEV_CTRL_SOFT_DISCONN 0x00000400 // soft disconnect
180#define USB_DEV_CTRL_SCALEDOWN 0x00000800 // for simulation speedup
181#define USB_DEV_CTRL_DEVNAK 0x00001000 // set nak on all OUT EPs
182#define USB_DEV_CTRL_APCSR_DONE 0x00002000 // set to signal CSR update
183#define USB_DEV_CTRL_MASK_BURST_LEN 0x000f0000 // mask for burst length
184#define USB_DEV_CTRL_MASK_THRESHOLD_LEN 0xff000000 // mask for threshold length
185
186/* settings of burst length for maskBurstLen_c field */
187/* amd 5536 datasheet: (BLEN+1) dwords */
188#define USB_DEV_CTRL_BLEN_1DWORD 0x00000000
189#define USB_DEV_CTRL_BLEN_2DWORDS 0x00010000
190#define USB_DEV_CTRL_BLEN_4DWORDS 0x00020000
191#define USB_DEV_CTRL_BLEN_8DWORDS 0x00030000
192#define USB_DEV_CTRL_BLEN_16DWORDS 0x00040000
193#define USB_DEV_CTRL_BLEN_32DWORDS 0x00050000
194#define USB_DEV_CTRL_BLEN_64DWORDS 0x00060000
195#define USB_DEV_CTRL_BLEN_128DWORDS 0x00070000
196#define USB_DEV_CTRL_BLEN_256DWORDS 0x00080000
197#define USB_DEV_CTRL_BLEN_512DWORDS 0x00090000
198
199/* settings of threshold length for maskThresholdLen_c field */
200/* amd 5536 datasheet: (TLEN+1) dwords */
201#define USB_DEV_CTRL_TLEN_1DWORD 0x00000000
202#define USB_DEV_CTRL_TLEN_HALFMAXSIZE 0x01000000
203#define USB_DEV_CTRL_TLEN_4THMAXSIZE 0x02000000
204#define USB_DEV_CTRL_TLEN_8THMAXSIZE 0x03000000
205
206#define USB_DEV_CFG_HS 0x00000000
207#define USB_DEV_CFG_FS 0x00000001 /* 30 or 60MHz */
208#define USB_DEV_CFG_LS 0x00000002
209#define USB_DEV_CFG_FS_48 0x00000003 /* 48MHz */
210#define USB_DEV_CFG_REMOTE_WAKEUP 0x00000004
211#define USB_DEV_CFG_SELF_POWERED 0x00000008
212#define USB_DEV_CFG_SYNC_FRAME 0x00000010
213#define USB_DEV_CFG_PI_16BIT 0x00000000
214#define USB_DEV_CFG_PI_8BIT 0x00000020
215#define USB_DEV_CFG_UNI_DIR 0x00000000
216#define USB_DEV_CFG_BI_DIR 0x00000040
217#define USB_DEV_CFG_STAT_ACK 0x00000000
218#define USB_DEV_CFG_STAT_STALL 0x00000080
219#define USB_DEV_CFG_PHY_ERR_DETECT 0x00000200 /* monitor phy for errors */
220#define USB_DEV_CFG_HALT_STAT 0x00010000 /* ENDPOINT_HALT supported */
221 /* 0: ACK, 1: STALL */
222#define USB_DEV_CFG_CSR_PRG 0x00020000
223#define USB_DEV_CFG_SET_DESC 0x00040000 /* SET_DESCRIPTOR supported */
224 /* 0: STALL, 1: pass on setup packet */
225#define USB_DEV_CFG_DMA_RESET 0x20000000
226#define USB_DEV_CFG_HNPSFEN 0x40000000
227#define USB_DEV_CFG_SOFT_RESET 0x80000000
228
229/* Device Status Register and bit fields */
230#define USB_DEV_STS_MASK_CFG 0x0000000f
231#define USB_DEV_STS_MASK_IF 0x000000f0
232#define USB_DEV_STS_MASK_ALT_SET 0x00000f00
233#define USB_DEV_STS_SUSPEND_STAT 0x00001000
234#define USB_DEV_STS_MASK_SPD 0x00006000 /* Enumerated Speed */
235#define USB_DEV_STS_SPD_HS 0x00000000
236#define USB_DEV_STS_SPD_FS 0x00002000
237#define USB_DEV_STS_SPD_LS 0x00004000
238#define USB_DEV_STS_RXF_EMPTY 0x00008000
239#define USB_DEV_STS_PHY_ERROR 0x00010000
240#define USB_DEV_STS_SESSVLD 0x00020000 /* session valid (vbus>1.2V) */
241#define USB_DEV_STS_MASK_FRM_NUM 0xfffc0000 /* SOF frame number */
242
243
244/* Device Intr Register and bit fields */
245#define USB_DEV_INTR_SET_CONFIG 0x00000001 /* set configuration cmd rcvd */
246#define USB_DEV_INTR_SET_INTERFACE 0x00000002 /* set interface command rcvd */
247#define USB_DEV_INTR_EARLY_SUSPEND 0x00000004 /* idle on usb for 3ms */
248#define USB_DEV_INTR_USB_RESET 0x00000008 /* usb bus reset req */
249#define USB_DEV_INTR_USB_SUSPEND 0x00000010 /* usb bus suspend req */
250#define USB_DEV_INTR_SOF 0x00000020 /* SOF seen on bus */
251#define USB_DEV_INTR_ENUM_DONE 0x00000040 /* usb speed enum done */
252#define USB_DEV_INTR_SVC 0x00000080 /* USB_DEV_STS changed */
253
254/* EP Control Register Fields */
255#define USB_EP_CTRL_STALL 0x00000001
256#define USB_EP_CTRL_FLUSH 0x00000002 /* EP In data fifo Flush */
257#define USB_EP_CTRL_SNOOP_MODE 0x00000004 // snoop mode for out endpoint
258#define USB_EP_CTRL_PD 0x00000008 /* EP Poll Demand */
259#define USB_EP_CTRL_EPTYPE_MASK 0x00000030 // bit 5-4: endpoint types
260#define USB_EP_TYPE_CONTROL 0x00000000 // control endpoint
261#define USB_EP_TYPE_ISO 0x00000010 // isochronous endpoint
262#define USB_EP_TYPE_BULK 0x00000020 // bulk endpoint
263#define USB_EP_TYPE_INTERRUPT 0x00000030 // interrupt endpoint
264#define USB_EP_CTRL_NAK 0x00000040 /* EP NAK Status */
265#define USB_EP_CTRL_SNAK 0x00000080 /* EP Set NAK Bit */
266#define USB_EP_CTRL_CNAK 0x00000100 /* EP Clr NAK Bit */
267#define USB_EP_CTRL_ACT 0x00000400 /* EP Clr NAK Bit */
268
269/* bit fields in EP Status Register */
270#define USB_EP_STAT_OUT_RCVD 0x00000010 /* OUT token received */
271#define USB_EP_STAT_SETUP_RCVD 0x00000020 /* SETUP token received */
272#define USB_EP_STAT_IN 0x00000040 /* IN token received? */
273#define USB_EP_STAT_BNA 0x00000080 /* Buffer Not Available */
274#define USB_EP_STAT_BUFF_ERROR 0x00000100
275#define USB_EP_STAT_HERR 0x00000200 /* Host Error */
276#define USB_EP_STAT_AHB_ERROR 0x00000200
277#define USB_EP_STAT_TDC 0x00000400 /* Transmit DMA Complete */
278
279/*-------------------------*/
280/* DMA Related Definitions */
281/*-------------------------*/
282
283/* dma status */
284#define USB_DMA_DESC_BUFF_STS 0x80000000 /* Buffer Status */
285#define USB_DMA_DESC_BS_HST_RDY 0x80000000 /* Host Ready */
286#define USB_DMA_DESC_BS_DMA_DONE 0x00000000 /* DMA Done */
287#define USB_DMA_DESC_ZERO_LEN 0x40000000 /* zero length packet */
288#define USB_DMA_DESC_EARY_INTR 0x20000000 /* early interrupt */
289#define USB_DMA_DESC_RXTX_STS 0x10000000
290#define USB_DMA_DESC_RTS_SUCC 0x00000000 /* Success */
291#define USB_DMA_DESC_RTS_BUFERR 0x10000000 /* Buffer Error */
292#define USB_DMA_DESC_LAST 0x08000000
293#define USB_DMA_DESC_MASK_FRAM_NUM 0x07ff0000 // bits 26-16: frame number for iso
294#define USB_DMA_DESC_RXTX_BYTES 0x0000FFFF
295
296/* setup descriptor */
297#define SETUP_MASK_CONFIG_STAT 0x0fff0000
298#define SETUP_MASK_CONFIG_NUM 0x0f000000
299#define SETUP_MASK_IF_NUM 0x00f00000
300#define SETUP_MASK_ALT_SETNUM 0x000f0000
301
302#define EP_STATE_ALLOCATED 0x00000001
303#define EP_STATE_BUSY 0x00000002
304#define EP_STATE_ASYNC 0x00000004
305
306struct usb_dev_dma_desc {
307 int status;
308 int resv;
309 void *data_ptr;
310 void *next_desc;
311};
312
313struct usb_dev_setup_buf {
314 int status;
315 int resv;
316 int data1; /* first 4 bytes of data */
317 int data2; /* last 4 bytes of data */
318};
319
320struct usb_endpoint
321{
322 void *buf;
323 unsigned int len;
324 volatile unsigned int state;
325 int rc;
326 struct wakeup complete;
327 struct usb_dev_dma_desc *uc_desc;
328};
329 40
330static struct usb_endpoint endpoints[USB_NUM_EPS][2]; 41static struct usb_endpoint endpoints[USB_NUM_EPS][2];
331 42
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 23:24:47 +0000