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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-05 04:48:43 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-05 04:48:43 +0000 |
commit | 7a90aa40c605ec27f6743e2dd3bb55d46495601a (patch) | |
tree | 2c774a7926363d96fe0d8066e7b2735ed5d73ff9 /firmware/target/arm/as3525/system-as3525.c | |
parent | 0eb888b23a5d27dd5b537b258e08e61ae87b6c2a (diff) | |
download | rockbox-7a90aa40c605ec27f6743e2dd3bb55d46495601a.tar.gz rockbox-7a90aa40c605ec27f6743e2dd3bb55d46495601a.zip |
as3525v2: set PCLK correctly
PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/system-as3525.c')
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 0d91d9cad4..feaf06aab1 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -290,7 +290,9 @@ void system_init(void) | |||
290 | /* Set PCLK frequency */ | 290 | /* Set PCLK frequency */ |
291 | CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ | 291 | CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ |
292 | (AS3525_PCLK_DIV0 << 2) | | 292 | (AS3525_PCLK_DIV0 << 2) | |
293 | #if CONFIG_CPU == AS3525 | ||
293 | (AS3525_PCLK_DIV1 << 6) | | 294 | (AS3525_PCLK_DIV1 << 6) | |
295 | #endif | ||
294 | AS3525_PCLK_SEL); | 296 | AS3525_PCLK_SEL); |
295 | 297 | ||
296 | #ifdef BOOTLOADER | 298 | #ifdef BOOTLOADER |
@@ -372,9 +374,16 @@ void set_cpu_frequency(long frequency) | |||
372 | "mcr p15, 0, r0, c1, c0 \n" | 374 | "mcr p15, 0, r0, c1, c0 \n" |
373 | : : : "r0" ); | 375 | : : : "r0" ); |
374 | #else | 376 | #else |
377 | /* AS3525v2 */ | ||
378 | int oldstatus = disable_irq_save(); | ||
379 | |||
380 | /* Change PCLK while FCLK is low, so it doesn't go too high */ | ||
381 | CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0 << 2); | ||
382 | |||
375 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | | 383 | CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | |
376 | (AS3525_FCLK_PREDIV << 2) | | 384 | (AS3525_FCLK_PREDIV << 2) | |
377 | AS3525_FCLK_SEL); | 385 | AS3525_FCLK_SEL); |
386 | restore_irq(oldstatus); | ||
378 | #endif /* CONFIG_CPU == AS3525 */ | 387 | #endif /* CONFIG_CPU == AS3525 */ |
379 | 388 | ||
380 | cpu_frequency = CPUFREQ_MAX; | 389 | cpu_frequency = CPUFREQ_MAX; |
@@ -388,9 +397,17 @@ void set_cpu_frequency(long frequency) | |||
388 | "mcr p15, 0, r0, c1, c0 \n" | 397 | "mcr p15, 0, r0, c1, c0 \n" |
389 | : : : "r0" ); | 398 | : : : "r0" ); |
390 | #else | 399 | #else |
400 | /* AS3525v2 */ | ||
401 | int oldstatus = disable_irq_save(); | ||
402 | |||
391 | CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) | | 403 | CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) | |
392 | (AS3525_FCLK_PREDIV << 2) | | 404 | (AS3525_FCLK_PREDIV << 2) | |
393 | AS3525_FCLK_SEL); | 405 | AS3525_FCLK_SEL); |
406 | |||
407 | /* Change PCLK after FCLK is low, so it doesn't go too high */ | ||
408 | CGU_PERI = (CGU_PERI & ~(0x1F << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2); | ||
409 | |||
410 | restore_irq(oldstatus); | ||
394 | #endif /* CONFIG_CPU == AS3525 */ | 411 | #endif /* CONFIG_CPU == AS3525 */ |
395 | 412 | ||
396 | #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE | 413 | #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE |