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authorRafaël Carré <rafael.carre@gmail.com>2010-02-05 12:40:25 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-02-05 12:40:25 +0000
commit12af2926e50450fe8a5aacbc1d4477b68fdd3e63 (patch)
treee761118345fc8640ba181999e8575964f3975587 /firmware/target/arm/as3525/system-as3525.c
parenta9ab407f8460017d3c7189f0cbf4bd464e7a90ce (diff)
downloadrockbox-12af2926e50450fe8a5aacbc1d4477b68fdd3e63.tar.gz
rockbox-12af2926e50450fe8a5aacbc1d4477b68fdd3e63.zip
Make Clip+ bootloader build
Now making the Fuzev2 bootloader build should be pretty easy TODO: - write button driver (FlynDice found all buttons already) - find button light - decide if lcd-ssd1303.c must be modified for Clip+ using SSP or forked - check if backlight code works (I copied Clipv2 code) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24520 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/system-as3525.c')
-rw-r--r--firmware/target/arm/as3525/system-as3525.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 2e6b6d4085..6c3299eea3 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -205,7 +205,8 @@ static void sdram_init(void)
205/* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */ 205/* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
206#define MEMORY_MODEL 0x21 206#define MEMORY_MODEL 0x21
207 207
208#elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) 208#elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \
209 || defined(SANSA_CLIPPLUS)
209/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */ 210/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
210#define MEMORY_MODEL 0x5 211#define MEMORY_MODEL 0x5
211 212
@@ -256,7 +257,7 @@ void memory_init(void)
256 257
257void system_init(void) 258void system_init(void)
258{ 259{
259#ifdef SANSA_CLIPV2 260#if CONFIG_CPU == AS3525v2
260 /* Init procedure isn't fully understood yet 261 /* Init procedure isn't fully understood yet
261 * CCU_* registers differ from AS3525 262 * CCU_* registers differ from AS3525
262 */ 263 */
@@ -270,7 +271,7 @@ void system_init(void)
270 CGU_PERI &= ~0x7f; /* pclk 24 MHz */ 271 CGU_PERI &= ~0x7f; /* pclk 24 MHz */
271 CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2) 272 CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
272 | 1; /* clk_in = PLLA */ 273 | 1; /* clk_in = PLLA */
273#else /* SANSA_CLIPV2 */ 274#else
274 unsigned int reset_loops = 640; 275 unsigned int reset_loops = 640;
275 276
276 CCU_SRC = 0x1fffff0 277 CCU_SRC = 0x1fffff0
@@ -315,7 +316,7 @@ void system_init(void)
315 sdram_init(); 316 sdram_init();
316#endif /* BOOTLOADER */ 317#endif /* BOOTLOADER */
317 318
318#endif /* SANSA_CLIPV2 */ 319#endif /* CONFIG_CPU == AS3525v2 */
319 320
320#if 0 /* the GPIO clock is already enabled by the dualboot function */ 321#if 0 /* the GPIO clock is already enabled by the dualboot function */
321 CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; 322 CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;