As3525 v1/v2 Add power savings menu

Allow user to select cpu undervolt

There have been quite a few issues across the SANSA AMS line related
to CPU undervolting while most players show greatly increased runtime
some crash.
Rather than constanly upping the voltage we now have a
setting with a safe value for all players and the option for lower voltages

I plan to add a few other options here later such as disk
timings and maybe some other clocks/experimental settings

Added: Disk Low speed option for AS3525v2 devices cuts
	frequency to 12 MHz from 24 MHz
Added: Disk Low speed option for AS3525v1 devices cuts
        frequency to 15.5 MHz from 31 MHz

Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices

Fixed: Debug menu for AS3525v2 No SDSLOT frequency,
	Showed IDE freq though it is unused

Added: DBOP and SSP underclocking affects display on v1/v2 respectively

Fixed: debug menu now has SSP frequency, and SSP_CPSR

Update: made settings menu more generic

Update: cleaned up code

Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE.
	not sure why but,  waiting on testing to confirm

Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE.

Fixed: v1 devices don't like display timing set lower (dbop)
       v1 devices don't have a divider set for ssp (causes divide by 0)

Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32

Fixed: v1 devices didn't work properly with highspeed sd cards
	Added code from http://gerrit.rockbox.org/r/#/c/1704/
	Added powersave and IDE interface enable/disable

Added: V2 devices now have powersave enabled on sd interface

Update: cleaned up code, lang defines, added manual entries

Update ssp clock mechanism added calculated ssp divider to clipzip

Update turn display clock off when clip+ turns off display

Fixed: clipzip wrong register for SSP clock

Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b
TODO: add other players?

1 files changed, 25 insertions, 1 deletions

diff --git a/firmware/target/arm/as3525/sd-as3525v2.c b/firmware/target/arm/as3525/sd-as3525v2.c
index b512cc2ea4..d27df5289c 100644
--- a/firmware/target/arm/as3525/sd-as3525v2.c
+++ b/firmware/target/arm/as3525/sd-as3525v2.c
@@ -488,7 +488,7 @@ static int sd_init_card(const int drive)
     card_info[drive].initialized = 0;
     card_info[drive].rca = 0;
 
-    /*  assume 24 MHz clock / 60 = 400 kHz  */
+    /*  assume 24 MHz clock / (2x)60 = 200 kHz  */
     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 
     /* 100 - 400kHz clock required for Identification Mode  */
@@ -957,3 +957,27 @@ int sd_event(long id, intptr_t data)
 
     return rc;
 }
+
+#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISK)
+/* declared in system-as3525.c */
+void ams_sd_set_low_speed(bool slow)
+{
+    /* block access while speed is changed */
+    mutex_lock(&sd_mtx);
+    enable_controller(true);
+    if (slow)
+    {
+        CGU_SDSLOT = (CGU_SDSLOT & ~(0xF << 2)) | (AS3525_SDSLOT_DIV_MAX << 2);
+        /* power save is enabled for the sd card(s) ASSUMES CRD0 is int drive! */
+        MCI_CLKENA |= (CCLK_LP_CRD1 | CCLK_LP_CRD2 | CCLK_LP_CRD3);
+    }
+    else
+    {
+        /* Full Speed */
+        CGU_SDSLOT = (CGU_SDSLOT & ~(0xF << 2)) | (AS3525_SDSLOT_DIV << 2);
+        MCI_CLKENA = (MCI_CLKENA & ~(CCLK_LP_CRD1 | CCLK_LP_CRD2 | CCLK_LP_CRD3));
+    }
+    enable_controller(false);
+    mutex_unlock(&sd_mtx);
+}
+#endif