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author | William Wilgus <me.theuser@yahoo.com> | 2018-07-27 23:56:32 +0200 |
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committer | William Wilgus <me.theuser@yahoo.com> | 2018-07-27 23:56:32 +0200 |
commit | 6f0320a9535bc1aa81d83fa879ac14d5ee603658 (patch) | |
tree | 3b12fc361595ecd2249f391e114036cb30150105 /firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c | |
parent | 400603abdfb4ba7566e0cae8dbed9268f06716dc (diff) | |
download | rockbox-6f0320a9535bc1aa81d83fa879ac14d5ee603658.tar.gz rockbox-6f0320a9535bc1aa81d83fa879ac14d5ee603658.zip |
As3525 v1/v2 Add power savings menu
Allow user to select cpu undervolt
There have been quite a few issues across the SANSA AMS line related
to CPU undervolting while most players show greatly increased runtime
some crash.
Rather than constanly upping the voltage we now have a
setting with a safe value for all players and the option for lower voltages
I plan to add a few other options here later such as disk
timings and maybe some other clocks/experimental settings
Added: Disk Low speed option for AS3525v2 devices cuts
frequency to 12 MHz from 24 MHz
Added: Disk Low speed option for AS3525v1 devices cuts
frequency to 15.5 MHz from 31 MHz
Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices
Fixed: Debug menu for AS3525v2 No SDSLOT frequency,
Showed IDE freq though it is unused
Added: DBOP and SSP underclocking affects display on v1/v2 respectively
Fixed: debug menu now has SSP frequency, and SSP_CPSR
Update: made settings menu more generic
Update: cleaned up code
Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE.
not sure why but, waiting on testing to confirm
Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE.
Fixed: v1 devices don't like display timing set lower (dbop)
v1 devices don't have a divider set for ssp (causes divide by 0)
Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32
Fixed: v1 devices didn't work properly with highspeed sd cards
Added code from http://gerrit.rockbox.org/r/#/c/1704/
Added powersave and IDE interface enable/disable
Added: V2 devices now have powersave enabled on sd interface
Update: cleaned up code, lang defines, added manual entries
Update ssp clock mechanism added calculated ssp divider to clipzip
Update turn display clock off when clip+ turns off display
Fixed: clipzip wrong register for SSP clock
Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b
TODO: add other players?
Diffstat (limited to 'firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c')
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c index e17bfc421b..8a3df517fb 100644 --- a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c +++ b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c | |||
@@ -35,12 +35,26 @@ static int lcd_type; | |||
35 | static bool lcd_enabled; | 35 | static bool lcd_enabled; |
36 | #endif | 36 | #endif |
37 | 37 | ||
38 | static void ssp_set_prescaler(unsigned int prescaler) | ||
39 | { | ||
40 | int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
41 | /* must be on to write regs */ | ||
42 | bool ssp_enabled = bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE) & | ||
43 | CGU_SSP_CLOCK_ENABLE; | ||
44 | SSP_CPSR = prescaler; | ||
45 | |||
46 | if (!ssp_enabled) /* put it back how we found it */ | ||
47 | bitclr32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); | ||
48 | |||
49 | restore_irq(oldlevel); | ||
50 | } | ||
51 | |||
38 | /* initialises the host lcd hardware, returns the lcd type */ | 52 | /* initialises the host lcd hardware, returns the lcd type */ |
39 | static int lcd_hw_init(void) | 53 | static int lcd_hw_init(void) |
40 | { | 54 | { |
41 | /* configure SSP */ | 55 | /* configure SSP */ |
42 | bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); | 56 | bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); |
43 | SSP_CPSR = 4; /* TODO: use AS3525_SSP_PRESCALER, OF uses 8 */ | 57 | ssp_set_prescaler(AS3525_SSP_PRESCALER); /* OF = 0x8 */ |
44 | SSP_CR0 = (0 << 8) | /* SCR, serial clock rate divider = 1 */ | 58 | SSP_CR0 = (0 << 8) | /* SCR, serial clock rate divider = 1 */ |
45 | (1 << 7) | /* SPH, phase = 1 */ | 59 | (1 << 7) | /* SPH, phase = 1 */ |
46 | (1 << 6) | /* SPO, polarity = 1 */ | 60 | (1 << 6) | /* SPO, polarity = 1 */ |
@@ -437,3 +451,11 @@ void lcd_update(void) | |||
437 | { | 451 | { |
438 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); | 452 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); |
439 | } | 453 | } |
454 | |||
455 | #if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISP) | ||
456 | /* declared in system-as3525.c */ | ||
457 | void ams_ssp_set_low_speed(bool slow) | ||
458 | { | ||
459 | ssp_set_prescaler(slow ? AS3525_SSP_PRESCALER_MAX : AS3525_SSP_PRESCALER); | ||
460 | } | ||
461 | #endif | ||