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author | Jens Arnold <amiconn@rockbox.org> | 2010-06-04 23:12:33 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2010-06-04 23:12:33 +0000 |
commit | c4f88526c73b3da2bda03aa40de06b3535fe266b (patch) | |
tree | 94c25d98224fcf66657960ba9727471ab4239b1e /firmware/target/arm/as3525/sansa-clipplus | |
parent | fab86a6a4c8b82f8d1764b4dabc1127e1340f571 (diff) | |
download | rockbox-c4f88526c73b3da2bda03aa40de06b3535fe266b.tar.gz rockbox-c4f88526c73b3da2bda03aa40de06b3535fe266b.zip |
Port greylib blitting optimisation to clipv2 and Clip+. Actual speedup can't be measured because something is fishy with the cpu clocking (calculated load is negative??)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26562 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/sansa-clipplus')
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipplus/lcd-as-clip-plus.S | 45 |
1 files changed, 15 insertions, 30 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipplus/lcd-as-clip-plus.S b/firmware/target/arm/as3525/sansa-clipplus/lcd-as-clip-plus.S index 4ffbb9252c..7dcdc9f0da 100644 --- a/firmware/target/arm/as3525/sansa-clipplus/lcd-as-clip-plus.S +++ b/firmware/target/arm/as3525/sansa-clipplus/lcd-as-clip-plus.S | |||
@@ -56,43 +56,28 @@ lcd_grey_data: | |||
56 | ldr lr, =SSP_BASE | 56 | ldr lr, =SSP_BASE |
57 | 57 | ||
58 | .greyloop: | 58 | .greyloop: |
59 | ldmia r1, {r3-r4} /* Fetch 8 pixel phases */ | 59 | ldmia r1, {r3-r4} |
60 | ldmia r0!, {r5-r6} /* Fetch 8 pixel values */ | 60 | |
61 | 61 | and r5, r12, r3 @ r5 = 3.......2.......1.......0....... | |
62 | mov r7, #0 | 62 | and r6, r12, r4 @ r6 = 7.......6.......5.......4....... |
63 | 63 | orr r5, r5, r6, lsr #4 @ r5 = 3...7...2...6...1...5...0...4... | |
64 | /* set bits 7..4 */ | 64 | orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..12..56..01..45.. |
65 | tst r3, #0x80 | 65 | orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.012.456. |
66 | orrne r7, r7, #0x80 | 66 | orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.01234567 |
67 | tst r3, #0x8000 | 67 | |
68 | orrne r7, r7, #0x40 | 68 | ldmia r0!, {r6-r7} |
69 | tst r3, #0x800000 | ||
70 | orrne r7, r7, #0x20 | ||
71 | tst r3, #0x80000000 | ||
72 | orrne r7, r7, #0x10 | ||
73 | bic r3, r3, r12 | 69 | bic r3, r3, r12 |
74 | add r3, r3, r5 | 70 | add r3, r3, r6 |
75 | |||
76 | /* set bits 3..0 */ | ||
77 | tst r4, #0x80 | ||
78 | orrne r7, r7, #0x08 | ||
79 | tst r4, #0x8000 | ||
80 | orrne r7, r7, #0x04 | ||
81 | tst r4, #0x800000 | ||
82 | orrne r7, r7, #0x02 | ||
83 | tst r4, #0x80000000 | ||
84 | orrne r7, r7, #0x01 | ||
85 | bic r4, r4, r12 | 71 | bic r4, r4, r12 |
86 | add r4, r4, r6 | 72 | add r4, r4, r7 |
87 | |||
88 | stmia r1!, {r3-r4} | 73 | stmia r1!, {r3-r4} |
89 | 74 | ||
90 | 1: | 75 | 1: |
91 | ldr r5, [lr, #0xC] @ SSP_SR | 76 | ldr r6, [lr, #0xC] @ SSP_SR |
92 | ands r5, r5, #(1<<1) @ wait until transmit fifo isn't full | 77 | ands r6, r6, #(1<<1) @ wait until transmit fifo isn't full |
93 | beq 1b | 78 | beq 1b |
94 | 79 | ||
95 | strb r7, [lr, #0x08] @ SSP_DATA | 80 | strb r5, [lr, #0x08] @ SSP_DATA |
96 | 81 | ||
97 | subs r2, r2, #1 | 82 | subs r2, r2, #1 |
98 | bne .greyloop | 83 | bne .greyloop |