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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-26 16:02:00 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-26 16:02:00 +0000 |
commit | a39e4e9962109e77482d85609fbc452bd163e620 (patch) | |
tree | ebabb96a3d45a71a9a9aa6e332fe51dd4c4e0600 /firmware/target/arm/as3525/dma-pl081.c | |
parent | aaaf609996bf8e5c651fcf3aa20399a27f953cbc (diff) | |
download | rockbox-a39e4e9962109e77482d85609fbc452bd163e620.tar.gz rockbox-a39e4e9962109e77482d85609fbc452bd163e620.zip |
Sansa AMS: use non-busy wakeup to signal end of DMA transfer
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19233 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/dma-pl081.c')
-rw-r--r-- | firmware/target/arm/as3525/dma-pl081.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/firmware/target/arm/as3525/dma-pl081.c b/firmware/target/arm/as3525/dma-pl081.c index 31021e1560..fbe488ce05 100644 --- a/firmware/target/arm/as3525/dma-pl081.c +++ b/firmware/target/arm/as3525/dma-pl081.c | |||
@@ -19,21 +19,30 @@ | |||
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include <stdbool.h> | ||
22 | #include "as3525.h" | 23 | #include "as3525.h" |
23 | #include "pl081.h" | 24 | #include "pl081.h" |
24 | #include "dma-target.h" | 25 | #include "dma-target.h" |
25 | #include <stdbool.h> | ||
26 | #include "panic.h" | 26 | #include "panic.h" |
27 | #include "kernel.h" | ||
27 | 28 | ||
28 | volatile bool dma_finished; | 29 | static struct wakeup transfer_completion_signal[2]; /* 2 channels */ |
30 | |||
31 | inline void dma_wait_transfer(int channel) | ||
32 | { | ||
33 | wakeup_wait(&transfer_completion_signal[channel], TIMEOUT_BLOCK); | ||
34 | } | ||
29 | 35 | ||
30 | void dma_init(void) | 36 | void dma_init(void) |
31 | { | 37 | { |
32 | /* Enable DMA controller */ | 38 | /* Enable DMA controller */ |
33 | CGU_PERI |= CGU_DMA_CLOCK_ENABLE; | 39 | CGU_PERI |= CGU_DMA_CLOCK_ENABLE; |
34 | DMAC_CONFIGURATION |= (1<<0); | 40 | DMAC_CONFIGURATION |= (1<<0); /* TODO: disable controller when not used */ |
35 | DMAC_SYNC = 0; | 41 | DMAC_SYNC = 0; |
36 | VIC_INT_ENABLE |= INTERRUPT_DMAC; | 42 | VIC_INT_ENABLE |= INTERRUPT_DMAC; |
43 | |||
44 | wakeup_init(&transfer_completion_signal[0]); | ||
45 | wakeup_init(&transfer_completion_signal[1]); | ||
37 | } | 46 | } |
38 | 47 | ||
39 | void dma_enable_channel(int channel, void *src, void *dst, int peri, | 48 | void dma_enable_channel(int channel, void *src, void *dst, int peri, |
@@ -65,8 +74,6 @@ void dma_enable_channel(int channel, void *src, void *dst, int peri, | |||
65 | 74 | ||
66 | DMAC_CH_CONTROL(channel) = control; | 75 | DMAC_CH_CONTROL(channel) = control; |
67 | 76 | ||
68 | dma_finished = false; | ||
69 | |||
70 | /* only needed if DMAC and Peripheral do not run at the same clock speed */ | 77 | /* only needed if DMAC and Peripheral do not run at the same clock speed */ |
71 | DMAC_SYNC |= (1<<peri); | 78 | DMAC_SYNC |= (1<<peri); |
72 | 79 | ||
@@ -92,5 +99,5 @@ void INT_DMAC(void) | |||
92 | 99 | ||
93 | DMAC_INT_TC_CLEAR |= (1<<channel); /* clear terminal count interrupt */ | 100 | DMAC_INT_TC_CLEAR |= (1<<channel); /* clear terminal count interrupt */ |
94 | 101 | ||
95 | dma_finished = true; /* TODO : use struct wakeup ? */ | 102 | wakeup_signal(&transfer_completion_signal[channel]); |
96 | } | 103 | } |