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author | Fred Bauer <fred.w.bauer@gmail.com> | 2010-12-29 16:07:15 +0000 |
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committer | Fred Bauer <fred.w.bauer@gmail.com> | 2010-12-29 16:07:15 +0000 |
commit | e541c98a7e19f22ab62a0adb370ea9f4c922e666 (patch) | |
tree | 74aa302fcc9e3c1ea05c9f45ad1724da8badd71e /firmware/target/arm/as3525/clock-target.h | |
parent | 7f31e38ac12884db251734482e0d37174c62e40b (diff) | |
download | rockbox-e541c98a7e19f22ab62a0adb370ea9f4c922e666.tar.gz rockbox-e541c98a7e19f22ab62a0adb370ea9f4c922e666.zip |
revert r28834 because it causes problems with uSD
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28925 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 135164b25b..97d6edb3d1 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -114,19 +114,17 @@ | |||
114 | /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ | 114 | /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ |
115 | //#define AS3525_PLLA_SETTING 0x2630 | 115 | //#define AS3525_PLLA_SETTING 0x2630 |
116 | 116 | ||
117 | #define AS3525_FCLK_PREDIV 2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ | 117 | #define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ |
118 | /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ | 118 | /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ |
119 | 119 | ||
120 | #define AS3525_FCLK_FREQ 186000000 /* Boosted FCLK frequency - over 200MHz */ | 120 | #define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ |
121 | /* requires CVDDp bumped to 1.2V */ | 121 | #define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ |
122 | #define AS3525_DRAM_FREQ 31000000 /* Initial DRAM frequency */ | ||
123 | #define AS3525_DRAM_FREQ_BOOSTED 62000000 | ||
124 | /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ | 122 | /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ |
125 | 123 | ||
126 | #endif /* CONFIG_CPU == AS3525v2 */ | 124 | #endif /* CONFIG_CPU == AS3525v2 */ |
127 | 125 | ||
128 | #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ | 126 | #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ |
129 | #define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1) | 127 | |
130 | #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ | 128 | #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ |
131 | 129 | ||
132 | /** ****************************************************************************/ | 130 | /** ****************************************************************************/ |
@@ -171,9 +169,6 @@ | |||
171 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ | 169 | /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ |
172 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ | 170 | #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ |
173 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ | 171 | #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ |
174 | #define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1) | ||
175 | #define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1) | ||
176 | |||
177 | #else | 172 | #else |
178 | 173 | ||
179 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK | 174 | #define AS3525_PCLK_SEL AS3525_CLK_FCLK |
@@ -184,10 +179,8 @@ | |||
184 | /* PCLK as Source */ | 179 | /* PCLK as Source */ |
185 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 180 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |
186 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) | 181 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) |
187 | #define AS3525_I2C_PRESCALER_BOOSTED CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ) | ||
188 | #define AS3525_I2C_FREQ 400000 | 182 | #define AS3525_I2C_FREQ 400000 |
189 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | 183 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) |
190 | #define AS3525_SD_IDENT_DIV_BOOSTED ((CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_SD_IDENT_FREQ) / 2) - 1) | ||
191 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | 184 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ |
192 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ | 185 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ |
193 | #define AS3525_SSP_FREQ 12000000 | 186 | #define AS3525_SSP_FREQ 12000000 |