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author | William Wilgus <me.theuser@yahoo.com> | 2018-07-28 17:35:01 +0200 |
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committer | William Wilgus <me.theuser@yahoo.com> | 2018-07-28 17:35:07 +0200 |
commit | d8bd356e565f5d1be946462616e8bb1e858fb833 (patch) | |
tree | 71e60336b6e43fc372b2f56941cdc4a4bf054659 /firmware/target/arm/as3525/clock-target.h | |
parent | 16f10e2abddb3a6cb6e3a7098ff0c190c0635401 (diff) | |
download | rockbox-d8bd356e565f5d1be946462616e8bb1e858fb833.tar.gz rockbox-d8bd356e565f5d1be946462616e8bb1e858fb833.zip |
Revert "As3525 v1/v2 Add power savings menu"
This reverts commit 6f0320a9535bc1aa81d83fa879ac14d5ee603658.
Change-Id: I7425d422a4a0af7a49e9194cfe0bb55d431bc401
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index c45529dfda..7f6b17eff4 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -158,32 +158,22 @@ | |||
158 | #endif /* CONFIG_CPU */ | 158 | #endif /* CONFIG_CPU */ |
159 | 159 | ||
160 | /* PCLK as Source */ | 160 | /* PCLK as Source */ |
161 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 161 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |
162 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) | 162 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) |
163 | #define AS3525_I2C_PRESCALER_MAX 0xFF | 0x300 /* Max value for prescaler */ | 163 | #define AS3525_I2C_FREQ 400000 |
164 | #define AS3525_I2C_FREQ 400000 | 164 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) |
165 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | 165 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ |
166 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | 166 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ |
167 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ | 167 | #define AS3525_SSP_FREQ 12000000 |
168 | #if LCD_DEPTH > 1 | ||
169 | #define AS3525_SSP_PRESCALER_MAX ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN) + 1) & ~1)/* must be an even number */ | ||
170 | #define AS3525_SSP_FREQ_MIN 2000000 /* 2 MHz gives a decent refresh rate on clipzip*/ | ||
171 | #else | ||
172 | #define AS3525_SSP_PRESCALER_MAX 0xFE & ~1 /*Max value for divider - must be an even number */ | ||
173 | #define AS3525_SSP_FREQ_MIN AS3525_SSP_FREQ /* No set minimum we just use max divider */ | ||
174 | #endif | ||
175 | #define AS3525_SSP_FREQ 12000000 | ||
176 | 168 | ||
177 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 169 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
178 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 170 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
179 | #define AS3525_IDE_DIV_MAX 0xF /* Max value for divider */ | ||
180 | 171 | ||
181 | #if CONFIG_CPU == AS3525v2 | 172 | #if CONFIG_CPU == AS3525v2 |
182 | #define AS3525_MS_FREQ 120000000 | 173 | #define AS3525_MS_FREQ 120000000 |
183 | #define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) | 174 | #define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) |
184 | #define AS3525_SDSLOT_FREQ 24000000 | 175 | #define AS3525_SDSLOT_FREQ 24000000 |
185 | #define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) | 176 | #define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) |
186 | #define AS3525_SDSLOT_DIV_MAX 0xF /* Max value for divider */ | ||
187 | #define AS3525_IDE_FREQ 80000000 | 177 | #define AS3525_IDE_FREQ 80000000 |
188 | #else | 178 | #else |
189 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ | 179 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ |
@@ -221,10 +211,6 @@ | |||
221 | #error SSP frequency is too low : clock divider will not fit ! | 211 | #error SSP frequency is too low : clock divider will not fit ! |
222 | #endif | 212 | #endif |
223 | 213 | ||
224 | #if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN)) + 1 ) & ~1) >= (1<<8) /* 8 bits */ | ||
225 | #error SSP_MIN frequency is too low : clock divider will not fit ! | ||
226 | #endif | ||
227 | |||
228 | /* AS3525_SD_IDENT_FREQ */ | 214 | /* AS3525_SD_IDENT_FREQ */ |
229 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 215 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
230 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 216 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |