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author | Jack Halpin <jack.halpin@gmail.com> | 2009-12-11 04:53:22 +0000 |
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committer | Jack Halpin <jack.halpin@gmail.com> | 2009-12-11 04:53:22 +0000 |
commit | c03871ab806755948cfb335d742b350ddeaa667d (patch) | |
tree | 9a1fb51bb8cc3ff4162c640e3f1678a2b998fec9 /firmware/target/arm/as3525/clock-target.h | |
parent | c0dc3c7a74e3eaaf28b3c18c5cdc3077a20e1dda (diff) | |
download | rockbox-c03871ab806755948cfb335d742b350ddeaa667d.tar.gz rockbox-c03871ab806755948cfb335d742b350ddeaa667d.zip |
Sansa AMS: Assume IDE_CLK is used as MCLK for internal SD. We assumed PCLK previously.
This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.
Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 81926c1884..bc112fdea8 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -118,9 +118,8 @@ | |||
118 | 118 | ||
119 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 119 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
120 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 120 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
121 | #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq | 121 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ |
122 | but sd transfers fail on some | 122 | |
123 | players with this limit */ | ||
124 | 123 | ||
125 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ | 124 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ |
126 | //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ | 125 | //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ |