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author | William Wilgus <me.theuser@yahoo.com> | 2018-07-27 23:56:32 +0200 |
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committer | William Wilgus <me.theuser@yahoo.com> | 2018-07-27 23:56:32 +0200 |
commit | 6f0320a9535bc1aa81d83fa879ac14d5ee603658 (patch) | |
tree | 3b12fc361595ecd2249f391e114036cb30150105 /firmware/target/arm/as3525/clock-target.h | |
parent | 400603abdfb4ba7566e0cae8dbed9268f06716dc (diff) | |
download | rockbox-6f0320a9535bc1aa81d83fa879ac14d5ee603658.tar.gz rockbox-6f0320a9535bc1aa81d83fa879ac14d5ee603658.zip |
As3525 v1/v2 Add power savings menu
Allow user to select cpu undervolt
There have been quite a few issues across the SANSA AMS line related
to CPU undervolting while most players show greatly increased runtime
some crash.
Rather than constanly upping the voltage we now have a
setting with a safe value for all players and the option for lower voltages
I plan to add a few other options here later such as disk
timings and maybe some other clocks/experimental settings
Added: Disk Low speed option for AS3525v2 devices cuts
frequency to 12 MHz from 24 MHz
Added: Disk Low speed option for AS3525v1 devices cuts
frequency to 15.5 MHz from 31 MHz
Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices
Fixed: Debug menu for AS3525v2 No SDSLOT frequency,
Showed IDE freq though it is unused
Added: DBOP and SSP underclocking affects display on v1/v2 respectively
Fixed: debug menu now has SSP frequency, and SSP_CPSR
Update: made settings menu more generic
Update: cleaned up code
Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE.
not sure why but, waiting on testing to confirm
Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE.
Fixed: v1 devices don't like display timing set lower (dbop)
v1 devices don't have a divider set for ssp (causes divide by 0)
Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32
Fixed: v1 devices didn't work properly with highspeed sd cards
Added code from http://gerrit.rockbox.org/r/#/c/1704/
Added powersave and IDE interface enable/disable
Added: V2 devices now have powersave enabled on sd interface
Update: cleaned up code, lang defines, added manual entries
Update ssp clock mechanism added calculated ssp divider to clipzip
Update turn display clock off when clip+ turns off display
Fixed: clipzip wrong register for SSP clock
Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b
TODO: add other players?
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 7f6b17eff4..c45529dfda 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -158,22 +158,32 @@ | |||
158 | #endif /* CONFIG_CPU */ | 158 | #endif /* CONFIG_CPU */ |
159 | 159 | ||
160 | /* PCLK as Source */ | 160 | /* PCLK as Source */ |
161 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 161 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |
162 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) | 162 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) |
163 | #define AS3525_I2C_FREQ 400000 | 163 | #define AS3525_I2C_PRESCALER_MAX 0xFF | 0x300 /* Max value for prescaler */ |
164 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | 164 | #define AS3525_I2C_FREQ 400000 |
165 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | 165 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) |
166 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ | 166 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ |
167 | #define AS3525_SSP_FREQ 12000000 | 167 | #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ |
168 | #if LCD_DEPTH > 1 | ||
169 | #define AS3525_SSP_PRESCALER_MAX ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN) + 1) & ~1)/* must be an even number */ | ||
170 | #define AS3525_SSP_FREQ_MIN 2000000 /* 2 MHz gives a decent refresh rate on clipzip*/ | ||
171 | #else | ||
172 | #define AS3525_SSP_PRESCALER_MAX 0xFE & ~1 /*Max value for divider - must be an even number */ | ||
173 | #define AS3525_SSP_FREQ_MIN AS3525_SSP_FREQ /* No set minimum we just use max divider */ | ||
174 | #endif | ||
175 | #define AS3525_SSP_FREQ 12000000 | ||
168 | 176 | ||
169 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 177 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
170 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 178 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
179 | #define AS3525_IDE_DIV_MAX 0xF /* Max value for divider */ | ||
171 | 180 | ||
172 | #if CONFIG_CPU == AS3525v2 | 181 | #if CONFIG_CPU == AS3525v2 |
173 | #define AS3525_MS_FREQ 120000000 | 182 | #define AS3525_MS_FREQ 120000000 |
174 | #define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) | 183 | #define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) |
175 | #define AS3525_SDSLOT_FREQ 24000000 | 184 | #define AS3525_SDSLOT_FREQ 24000000 |
176 | #define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) | 185 | #define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) |
186 | #define AS3525_SDSLOT_DIV_MAX 0xF /* Max value for divider */ | ||
177 | #define AS3525_IDE_FREQ 80000000 | 187 | #define AS3525_IDE_FREQ 80000000 |
178 | #else | 188 | #else |
179 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ | 189 | #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ |
@@ -211,6 +221,10 @@ | |||
211 | #error SSP frequency is too low : clock divider will not fit ! | 221 | #error SSP frequency is too low : clock divider will not fit ! |
212 | #endif | 222 | #endif |
213 | 223 | ||
224 | #if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN)) + 1 ) & ~1) >= (1<<8) /* 8 bits */ | ||
225 | #error SSP_MIN frequency is too low : clock divider will not fit ! | ||
226 | #endif | ||
227 | |||
214 | /* AS3525_SD_IDENT_FREQ */ | 228 | /* AS3525_SD_IDENT_FREQ */ |
215 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ | 229 | #if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ |
216 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! | 230 | #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! |