summaryrefslogtreecommitdiff
path: root/firmware/target/arm/as3525/ata_sd_as3525.c
diff options
context:
space:
mode:
authorJack Halpin <jack.halpin@gmail.com>2009-12-11 04:53:22 +0000
committerJack Halpin <jack.halpin@gmail.com>2009-12-11 04:53:22 +0000
commitc03871ab806755948cfb335d742b350ddeaa667d (patch)
tree9a1fb51bb8cc3ff4162c640e3f1678a2b998fec9 /firmware/target/arm/as3525/ata_sd_as3525.c
parentc0dc3c7a74e3eaaf28b3c18c5cdc3077a20e1dda (diff)
downloadrockbox-c03871ab806755948cfb335d742b350ddeaa667d.tar.gz
rockbox-c03871ab806755948cfb335d742b350ddeaa667d.zip
Sansa AMS: Assume IDE_CLK is used as MCLK for internal SD. We assumed PCLK previously.
This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller. Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card. Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct. Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip. Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz. Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525/ata_sd_as3525.c')
-rw-r--r--firmware/target/arm/as3525/ata_sd_as3525.c25
1 files changed, 19 insertions, 6 deletions
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c
index 472e0fe09a..ab247c86d9 100644
--- a/firmware/target/arm/as3525/ata_sd_as3525.c
+++ b/firmware/target/arm/as3525/ata_sd_as3525.c
@@ -121,6 +121,10 @@ static struct event_queue sd_queue;
121bool sd_enabled = false; 121bool sd_enabled = false;
122#endif 122#endif
123 123
124#if defined(HAVE_MULTIDRIVE)
125static bool hs_card = false;
126#endif
127
124static struct wakeup transfer_completion_signal; 128static struct wakeup transfer_completion_signal;
125static volatile unsigned int transfer_error[NUM_VOLUMES]; 129static volatile unsigned int transfer_error[NUM_VOLUMES];
126#define PL180_MAX_TRANSFER_ERRORS 10 130#define PL180_MAX_TRANSFER_ERRORS 10
@@ -347,13 +351,18 @@ static int sd_init_card(const int drive)
347 351
348 sd_parse_csd(&card_info[drive]); 352 sd_parse_csd(&card_info[drive]);
349 353
354#if defined(HAVE_MULTIDRIVE)
355 hs_card = (card_info[drive].speed == 50000000) ? true : false;
356#endif
357
350 /* Boost MCICLK to operating speed */ 358 /* Boost MCICLK to operating speed */
351 if(drive == INTERNAL_AS3525) 359 if(drive == INTERNAL_AS3525)
352 MCI_CLOCK(drive) = MCI_QUARTERSPEED; /* MCICLK = PCLK/4 = 15.5MHz */ 360 MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */
361#if defined(HAVE_MULTIDRIVE)
353 else 362 else
354 /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/ 363 /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
355 MCI_CLOCK(drive) = ((card_info[drive].speed == 50000000) ? 364 MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
356 MCI_HALFSPEED : MCI_QUARTERSPEED); 365#endif
357 366
358 /* CMD7 w/rca: Select card to put it in TRAN state */ 367 /* CMD7 w/rca: Select card to put it in TRAN state */
359 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL)) 368 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
@@ -733,10 +742,14 @@ static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
733 dma_enable_channel(0, dma_buf, MCI_FIFO(drive), 742 dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
734 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, 743 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
735 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); 744 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
736 745#if defined(HAVE_MULTIDRIVE)
737 /*Small delay for writes prevents data crc failures at lower freqs*/ 746 /*Small delay for writes prevents data crc failures at lower freqs*/
738 int write_delay = 125; 747 if((drive == SD_SLOT_AS3525) && !hs_card)
739 while(write_delay--); 748 {
749 int write_delay = 125;
750 while(write_delay--);
751 }
752#endif
740 } 753 }
741 else 754 else
742 dma_enable_channel(0, MCI_FIFO(drive), dma_buf, 755 dma_enable_channel(0, MCI_FIFO(drive), dma_buf,