As3525 v1/v2 Add power savings menu

Allow user to select cpu undervolt

There have been quite a few issues across the SANSA AMS line related
to CPU undervolting while most players show greatly increased runtime
some crash.
Rather than constanly upping the voltage we now have a
setting with a safe value for all players and the option for lower voltages

I plan to add a few other options here later such as disk
timings and maybe some other clocks/experimental settings

Added: Disk Low speed option for AS3525v2 devices cuts
	frequency to 12 MHz from 24 MHz
Added: Disk Low speed option for AS3525v1 devices cuts
        frequency to 15.5 MHz from 31 MHz

Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices

Fixed: Debug menu for AS3525v2 No SDSLOT frequency,
	Showed IDE freq though it is unused

Added: DBOP and SSP underclocking affects display on v1/v2 respectively

Fixed: debug menu now has SSP frequency, and SSP_CPSR

Update: made settings menu more generic

Update: cleaned up code

Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE.
	not sure why but,  waiting on testing to confirm

Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE.

Fixed: v1 devices don't like display timing set lower (dbop)
       v1 devices don't have a divider set for ssp (causes divide by 0)

Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32

Fixed: v1 devices didn't work properly with highspeed sd cards
	Added code from http://gerrit.rockbox.org/r/#/c/1704/
	Added powersave and IDE interface enable/disable

Added: V2 devices now have powersave enabled on sd interface

Update: cleaned up code, lang defines, added manual entries

Update ssp clock mechanism added calculated ssp divider to clipzip

Update turn display clock off when clip+ turns off display

Fixed: clipzip wrong register for SSP clock

Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b
TODO: add other players?

1 files changed, 26 insertions, 5 deletions

diff --git a/firmware/target/arm/as3525/ascodec-as3525.c b/firmware/target/arm/as3525/ascodec-as3525.c
index 14c3ee7a36..d23859e420 100644
--- a/firmware/target/arm/as3525/ascodec-as3525.c
+++ b/firmware/target/arm/as3525/ascodec-as3525.c
@@ -623,11 +623,25 @@ void i2c_init(void)
     /* required function but called too late for our needs */
 }
 
+static void i2c_set_prescaler(unsigned int prescaler)
+{
+    int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
+    /* must be on to write regs */
+    bool i2c_enabled = bitset32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE) &
+                                           CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE;
+
+    I2C2_CPSR0 = prescaler & 0xFF;          /* 8 lsb */
+    I2C2_CPSR1 = (prescaler >> 8) & 0x3;    /* 2 msb */
+
+    if (!i2c_enabled) /* put it back how we found it */
+        bitclr32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE);
+
+    restore_irq(oldlevel);
+}
+
 /* initialises the internal i2c bus and prepares for transfers to the codec */
 void ascodec_init(void)
 {
-    int prescaler;
-
     ll_init(&req_list);
     mutex_init(&as_mtx);
     ascodec_async_init(&as_audio_req, ascodec_int_audio_cb, 0);
@@ -637,9 +651,7 @@ void ascodec_init(void)
     bitset32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE);
 
     /* prescaler for i2c clock */
-    prescaler = AS3525_I2C_PRESCALER;
-    I2C2_CPSR0 = prescaler & 0xFF;          /* 8 lsb */
-    I2C2_CPSR1 = (prescaler >> 8) & 0x3;    /* 2 msb */
+    i2c_set_prescaler(AS3525_I2C_PRESCALER);
 
     /* set i2c slave address of codec part */
     I2C2_SLAD0 = AS3514_I2C_ADDR << 1;
@@ -690,3 +702,12 @@ void ams_i2c_get_debug_cpsr(unsigned int *i2c_cpsr)
 
     restore_irq(oldlevel);
 }
+
+#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_I2C)
+/* declared in system-as3525.c */
+void ams_i2c_set_low_speed(bool slow)
+{
+    i2c_set_prescaler(slow ? AS3525_I2C_PRESCALER_MAX : AS3525_I2C_PRESCALER);
+}
+#endif
+