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authorBarry Wardell <rockbox@barrywardell.net>2007-04-22 12:03:17 +0000
committerBarry Wardell <rockbox@barrywardell.net>2007-04-22 12:03:17 +0000
commitf43e50dc5333c096366a2a1cfd24728ea8030f62 (patch)
treed2701b71e2691ce3b6920bcd4032332d1b4af162 /firmware/system.c
parent0a643b8d9085f96e0c8ea267c12d634e2addf572 (diff)
downloadrockbox-f43e50dc5333c096366a2a1cfd24728ea8030f62.tar.gz
rockbox-f43e50dc5333c096366a2a1cfd24728ea8030f62.zip
Move PortalPlayer system.c code into the target tree.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13239 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/system.c')
-rw-r--r--firmware/system.c386
1 files changed, 0 insertions, 386 deletions
diff --git a/firmware/system.c b/firmware/system.c
index e4b11e8b79..badeb30e84 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -201,391 +201,5 @@ void UIE(unsigned int pc, unsigned int num)
201 } 201 }
202} 202}
203 203
204#if CONFIG_CPU==PP5020 || CONFIG_CPU==PP5024
205
206unsigned int ipod_hw_rev;
207
208#ifndef BOOTLOADER
209extern void TIMER1(void);
210extern void TIMER2(void);
211
212#if defined(IPOD_MINI) /* mini 1 only, mini 2G uses iPod 4G code */
213extern void ipod_mini_button_int(void);
214
215void irq(void)
216{
217 if(CURRENT_CORE == CPU)
218 {
219 if (CPU_INT_STAT & TIMER1_MASK)
220 TIMER1();
221 else if (CPU_INT_STAT & TIMER2_MASK)
222 TIMER2();
223 else if (CPU_HI_INT_STAT & GPIO_MASK)
224 ipod_mini_button_int();
225 } else {
226 if (COP_INT_STAT & TIMER1_MASK)
227 TIMER1();
228 else if (COP_INT_STAT & TIMER2_MASK)
229 TIMER2();
230 else if (COP_HI_INT_STAT & GPIO_MASK)
231 ipod_mini_button_int();
232 }
233}
234#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
235 || (defined SANSA_E200)
236/* TODO: this should really be in the target tree, but moving it there caused
237 crt0.S not to find it while linking */
238/* TODO: Even if it isn't in the target tree, this should be the default case */
239void irq(void)
240{
241 if(CURRENT_CORE == CPU)
242 {
243 if (CPU_INT_STAT & TIMER1_MASK)
244 TIMER1();
245 else if (CPU_INT_STAT & TIMER2_MASK)
246 TIMER2();
247 } else {
248 if (COP_INT_STAT & TIMER1_MASK)
249 TIMER1();
250 else if (COP_INT_STAT & TIMER2_MASK)
251 TIMER2();
252 }
253}
254#else
255extern void ipod_4g_button_int(void);
256
257void irq(void)
258{
259 if(CURRENT_CORE == CPU)
260 {
261 if (CPU_INT_STAT & TIMER1_MASK)
262 TIMER1();
263 else if (CPU_INT_STAT & TIMER2_MASK)
264 TIMER2();
265 else if (CPU_HI_INT_STAT & I2C_MASK)
266 ipod_4g_button_int();
267 } else {
268 if (COP_INT_STAT & TIMER1_MASK)
269 TIMER1();
270 else if (COP_INT_STAT & TIMER2_MASK)
271 TIMER2();
272 else if (COP_HI_INT_STAT & I2C_MASK)
273 ipod_4g_button_int();
274 }
275}
276#endif
277#endif /* BOOTLOADER */
278
279/* TODO: The following two function have been lifted straight from IPL, and
280 hence have a lot of numeric addresses used straight. I'd like to use
281 #defines for these, but don't know what most of them are for or even what
282 they should be named. Because of this I also have no way of knowing how
283 to extend the funtions to do alternate cache configurations and/or
284 some other CPU frequency scaling. */
285
286#ifndef BOOTLOADER
287static void ipod_init_cache(void)
288{
289/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
290 unsigned i;
291
292 /* cache init mode? */
293 CACHE_CTL = CACHE_INIT;
294
295 /* PP5002 has 8KB cache */
296 for (i = 0xf0004000; i < 0xf0006000; i += 16) {
297 outl(0x0, i);
298 }
299
300 outl(0x0, 0xf000f040);
301 outl(0x3fc0, 0xf000f044);
302
303 /* enable cache */
304 CACHE_CTL = CACHE_ENABLE;
305
306 for (i = 0x10000000; i < 0x10002000; i += 16)
307 inb(i);
308}
309#endif
310
311/* Not all iPod targets support CPU freq. boosting yet */
312#ifdef HAVE_ADJUSTABLE_CPU_FREQ
313void set_cpu_frequency(long frequency)
314{
315 unsigned long postmult;
316
317# if NUM_CORES > 1
318 /* Using mutex or spinlock isn't safe here. */
319 while (test_and_set(&boostctrl_mtx.locked, 1)) ;
320# endif
321
322 if (frequency == CPUFREQ_NORMAL)
323 postmult = CPUFREQ_NORMAL_MULT;
324 else if (frequency == CPUFREQ_MAX)
325 postmult = CPUFREQ_MAX_MULT;
326 else
327 postmult = CPUFREQ_DEFAULT_MULT;
328 cpu_frequency = frequency;
329
330 /* Enable PLL? */
331 outl(inl(0x70000020) | (1<<30), 0x70000020);
332
333 /* Select 24MHz crystal as clock source? */
334 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
335
336 /* Clock frequency = (24/8)*postmult */
337 outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
338
339 /* Wait for PLL relock? */
340 udelay(2000);
341
342 /* Select PLL as clock source? */
343 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
344
345# if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
346 /* We don't know why the timer interrupt gets disabled on the PP5020
347 based ipods, but without the following line, the 4Gs will freeze
348 when CPU frequency changing is enabled.
349
350 Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
351 elsewhere to enable interrupts) doesn't work, we need "|=".
352
353 It's not needed on the PP5021 and PP5022 ipods.
354 */
355
356 /* unmask interrupt source */
357 CPU_INT_EN |= TIMER1_MASK;
358 COP_INT_EN |= TIMER1_MASK;
359# endif
360
361# if NUM_CORES > 1
362 boostctrl_mtx.locked = 0;
363# endif
364}
365#elif !defined(BOOTLOADER)
366void ipod_set_cpu_frequency(void)
367{
368 /* Enable PLL? */
369 outl(inl(0x70000020) | (1<<30), 0x70000020);
370
371 /* Select 24MHz crystal as clock source? */
372 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
373
374 /* Clock frequency = (24/8)*25 = 75MHz */
375 outl(0xaa020000 | 8 | (25 << 8), 0x60006034);
376 /* Wait for PLL relock? */
377 udelay(2000);
378
379 /* Select PLL as clock source? */
380 outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
381}
382#endif
383
384void system_init(void)
385{
386#ifndef BOOTLOADER
387 if (CURRENT_CORE == CPU)
388 {
389 /* Remap the flash ROM from 0x00000000 to 0x20000000. */
390 MMAP3_LOGICAL = 0x20000000 | 0x3a00;
391 MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
392
393 /* The hw revision is written to the last 4 bytes of SDRAM by the
394 bootloader - we save it before Rockbox overwrites it. */
395 ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
396
397 /* disable all irqs */
398 COP_HI_INT_CLR = -1;
399 CPU_HI_INT_CLR = -1;
400 HI_INT_FORCED_CLR = -1;
401
402 COP_INT_CLR = -1;
403 CPU_INT_CLR = -1;
404 INT_FORCED_CLR = -1;
405
406# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
407 spinlock_init(&boostctrl_mtx);
408# endif
409
410#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
411 ipod_set_cpu_frequency();
412#endif
413 }
414#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
415 else
416 {
417 ipod_set_cpu_frequency();
418 }
419#endif
420 ipod_init_cache();
421#endif
422}
423
424void system_reboot(void)
425{
426 /* Reboot */
427 DEV_RS |= DEV_SYSTEM;
428}
429
430int system_memory_guard(int newmode)
431{
432 (void)newmode;
433 return 0;
434}
435#elif CONFIG_CPU==PP5002
436unsigned int ipod_hw_rev;
437#ifndef BOOTLOADER
438extern void TIMER1(void);
439extern void TIMER2(void);
440
441void irq(void)
442{
443 if(CURRENT_CORE == CPU)
444 {
445 if (CPU_INT_STAT & TIMER1_MASK)
446 TIMER1();
447 else if (CPU_INT_STAT & TIMER2_MASK)
448 TIMER2();
449 } else {
450 if (COP_INT_STAT & TIMER1_MASK)
451 TIMER1();
452 else if (COP_INT_STAT & TIMER2_MASK)
453 TIMER2();
454 }
455}
456
457#endif
458
459unsigned int current_core(void)
460{
461 if(((*(volatile unsigned long *)(0xc4000000)) & 0xff) == 0x55)
462 {
463 return CPU;
464 }
465 return COP;
466}
467
468
469/* TODO: The following two function have been lifted straight from IPL, and
470 hence have a lot of numeric addresses used straight. I'd like to use
471 #defines for these, but don't know what most of them are for or even what
472 they should be named. Because of this I also have no way of knowing how
473 to extend the funtions to do alternate cache configurations and/or
474 some other CPU frequency scaling. */
475
476#ifndef BOOTLOADER
477static void ipod_init_cache(void)
478{
479 int i =0;
480/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
481 outl(inl(0xcf004050) & ~0x700, 0xcf004050);
482 outl(0x4000, 0xcf004020);
483
484 outl(0x2, 0xcf004024);
485
486 /* PP5002 has 8KB cache */
487 for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) {
488 outl(0x0, i);
489 }
490
491 outl(0x0, 0xf000f020);
492 outl(0x3fc0, 0xf000f024);
493
494 outl(0x3, 0xcf004024);
495}
496
497#endif
498
499#ifdef HAVE_ADJUSTABLE_CPU_FREQ
500void set_cpu_frequency(long frequency)
501{
502 unsigned long postmult;
503
504 if (CURRENT_CORE == CPU)
505 {
506 if (frequency == CPUFREQ_NORMAL)
507 postmult = CPUFREQ_NORMAL_MULT;
508 else if (frequency == CPUFREQ_MAX)
509 postmult = CPUFREQ_MAX_MULT;
510 else
511 postmult = CPUFREQ_DEFAULT_MULT;
512 cpu_frequency = frequency;
513
514 outl(0x02, 0xcf005008);
515 outl(0x55, 0xcf00500c);
516 outl(0x6000, 0xcf005010);
517
518 /* Clock frequency = (24/8)*postmult */
519 outl(8, 0xcf005018);
520 outl(postmult, 0xcf00501c);
521
522 outl(0xe000, 0xcf005010);
523
524 /* Wait for PLL relock? */
525 udelay(2000);
526
527 /* Select PLL as clock source? */
528 outl(0xa8, 0xcf00500c);
529 }
530}
531#elif !defined(BOOTLOADER)
532static void ipod_set_cpu_speed(void)
533{
534 outl(0x02, 0xcf005008);
535 outl(0x55, 0xcf00500c);
536 outl(0x6000, 0xcf005010);
537#if 1
538 // 75 MHz (24/24 * 75) (default)
539 outl(24, 0xcf005018);
540 outl(75, 0xcf00501c);
541#endif
542
543#if 0
544 // 66 MHz (24/3 * 8)
545 outl(3, 0xcf005018);
546 outl(8, 0xcf00501c);
547#endif
548
549 outl(0xe000, 0xcf005010);
550
551 udelay(2000);
552
553 outl(0xa8, 0xcf00500c);
554}
555#endif
556
557void system_init(void)
558{
559#ifndef BOOTLOADER
560 if (CURRENT_CORE == CPU)
561 {
562 /* Remap the flash ROM from 0x00000000 to 0x20000000. */
563 MMAP3_LOGICAL = 0x20000000 | 0x3a00;
564 MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
565
566 ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
567 outl(-1, 0xcf00101c);
568 outl(-1, 0xcf001028);
569 outl(-1, 0xcf001038);
570#ifndef HAVE_ADJUSTABLE_CPU_FREQ
571 ipod_set_cpu_speed();
572#endif
573 }
574 ipod_init_cache();
575#endif
576}
577
578void system_reboot(void)
579{
580 outl(inl(0xcf005030) | 0x4, 0xcf005030);
581}
582
583int system_memory_guard(int newmode)
584{
585 (void)newmode;
586 return 0;
587}
588
589#endif /* CPU_ARM */ 204#endif /* CPU_ARM */
590#endif /* CONFIG_CPU */
591 205