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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-03-03 21:48:02 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-03-03 21:48:02 +0000 |
commit | 32160dc3c37aa470c4ab29dd59f8c5142c51c799 (patch) | |
tree | 1c22d32805205f235f08a717dd8b39ec4154ca3d /firmware/system.c | |
parent | 0de0162ebe6a823010e69e9a9428164ffbef674d (diff) | |
download | rockbox-32160dc3c37aa470c4ab29dd59f8c5142c51c799.tar.gz rockbox-32160dc3c37aa470c4ab29dd59f8c5142c51c799.zip |
iRiver: Increased the max CPU frequency to 120MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6125 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/system.c')
-rw-r--r-- | firmware/system.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/firmware/system.c b/firmware/system.c index 9fbce9e4b9..1cafc8f096 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -483,16 +483,16 @@ void set_cpu_frequency(long frequency) | |||
483 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass | 483 | DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass |
484 | frequency */ | 484 | frequency */ |
485 | PLLCR &= ~1; /* Bypass mode */ | 485 | PLLCR &= ~1; /* Bypass mode */ |
486 | PLLCR = 0x11c8600d; | 486 | PLLCR = 0x11853005; |
487 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 487 | CSCR0 = 0x00000980; /* Flash: 2 wait state */ |
488 | CSCR1 = 0x00001180; /* LCD: 4 wait states */ | 488 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ |
489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 489 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
490 | This may take up to 10ms! */ | 490 | This may take up to 10ms! */ |
491 | DCR = (DCR & ~0x000001ff) | 33; /* Refresh timer */ | 491 | DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ |
492 | cpu_frequency = CPUFREQ_MAX; | 492 | cpu_frequency = CPUFREQ_MAX; |
493 | tick_start(1000/HZ); | 493 | tick_start(1000/HZ); |
494 | IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ | 494 | IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ |
495 | IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (0 << 8); /* CS2wait */ | 495 | IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (1 << 8); /* CS2wait */ |
496 | break; | 496 | break; |
497 | 497 | ||
498 | case CPUFREQ_NORMAL: | 498 | case CPUFREQ_NORMAL: |