mips: Heavily rework DMA & caching code

Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70

1 files changed, 1 insertions, 1 deletions

diff --git a/firmware/rolo.c b/firmware/rolo.c
index de19c8e925..e60af46704 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -201,7 +201,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
         : : "r"(dest)
     );
 #elif defined(CPU_MIPS)
-    __dcache_writeback_all();
+    commit_discard_idcache();
     asm volatile(
         "jr     %0               \n"
         : : "r"(dest)