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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-18 15:55:56 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-18 15:55:56 +0000 |
commit | 4c5f25d5232d24ad8710bcdf8714c5a88622ce97 (patch) | |
tree | e663041eb7a94d9ee2691cbbaef9eb876fe52b5b /firmware/pcm_playback.c | |
parent | aa1042286aa05f04d1d832759d8ff18e8dea1113 (diff) | |
download | rockbox-4c5f25d5232d24ad8710bcdf8714c5a88622ce97.tar.gz rockbox-4c5f25d5232d24ad8710bcdf8714c5a88622ce97.zip |
iriver: set the S/PDIF Validity flag correctly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7189 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/pcm_playback.c')
-rw-r--r-- | firmware/pcm_playback.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c index da04795d80..3a68db4d0c 100644 --- a/firmware/pcm_playback.c +++ b/firmware/pcm_playback.c | |||
@@ -70,7 +70,7 @@ static void dma_start(const void *addr, long size) | |||
70 | /* Enable the FIFO and force one write to it */ | 70 | /* Enable the FIFO and force one write to it */ |
71 | IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; | 71 | IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; |
72 | /* Also send the audio to S/PDIF */ | 72 | /* Also send the audio to S/PDIF */ |
73 | EBU1CONFIG = 7 << 12 | 3 << 8 | 5 << 2; | 73 | EBU1CONFIG = (7 << 12) | (3 << 8) | (1 << 5) | (5 << 2); |
74 | DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START; | 74 | DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START; |
75 | } | 75 | } |
76 | 76 | ||
@@ -241,7 +241,7 @@ void pcm_play_pause(bool play) | |||
241 | //BCR0 = next_size; | 241 | //BCR0 = next_size; |
242 | /* Enable the FIFO and force one write to it */ | 242 | /* Enable the FIFO and force one write to it */ |
243 | IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; | 243 | IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; |
244 | EBU1CONFIG = 7 << 12 | 3 << 8 | 5 << 2; | 244 | EBU1CONFIG = (7 << 12) | (3 << 8) | (1 << 5) | (5 << 2); |
245 | DCR0 |= DMA_EEXT | DMA_START; | 245 | DCR0 |= DMA_EEXT | DMA_START; |
246 | 246 | ||
247 | uda1380_mute(false); | 247 | uda1380_mute(false); |