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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-07-16 12:25:27 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-07-16 12:25:27 +0000 |
commit | ffddab1e664ee9c0a1aec69f02a8ebfaeba3fb3e (patch) | |
tree | 70e8e8655208a51f303abb09c4be6a7b93cb1f57 /firmware/export | |
parent | dff382cb9c94f36246ed5aeea1ef4ddb26686588 (diff) | |
download | rockbox-ffddab1e664ee9c0a1aec69f02a8ebfaeba3fb3e.tar.gz rockbox-ffddab1e664ee9c0a1aec69f02a8ebfaeba3fb3e.zip |
Use register defines
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18068 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/r61509.h | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/firmware/export/r61509.h b/firmware/export/r61509.h new file mode 100644 index 0000000000..ca966ee781 --- /dev/null +++ b/firmware/export/r61509.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Maurus Cuelenaere | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /* | ||
23 | * Register definitions for the Renesas R61509 TFT Panel | ||
24 | */ | ||
25 | #ifndef __R61509_H | ||
26 | #define __R61509_H | ||
27 | |||
28 | /* Register list */ | ||
29 | #define REG_DRIVER_OUTPUT 0x001 | ||
30 | #define REG_LCD_DR_WAVE_CTRL 0x002 | ||
31 | #define REG_ENTRY_MODE 0x003 | ||
32 | #define REG_DISP_CTRL1 0x007 | ||
33 | #define REG_DISP_CTRL2 0x008 | ||
34 | #define REG_DISP_CTRL3 0x009 | ||
35 | #define REG_LPCTRL 0x00B | ||
36 | #define REG_EXT_DISP_CTRL1 0x00C | ||
37 | #define REG_EXT_DISP_CTRL2 0x00F | ||
38 | #define REG_PAN_INTF_CTRL1 0x010 | ||
39 | #define REG_PAN_INTF_CTRL2 0x011 | ||
40 | #define REG_PAN_INTF_CTRL3 0x012 | ||
41 | #define REG_PAN_INTF_CTRL4 0x020 | ||
42 | #define REG_PAN_INTF_CTRL5 0x021 | ||
43 | #define REG_PAN_INTF_CTRL6 0x022 | ||
44 | #define REG_FRM_MRKR_CTRL 0x090 | ||
45 | |||
46 | #define REG_PWR_CTRL1 0x100 | ||
47 | #define REG_PWR_CTRL2 0x101 | ||
48 | #define REG_PWR_CTRL3 0x102 | ||
49 | #define REG_PWR_CTRL4 0x103 | ||
50 | #define REG_PWR_CTRL5 0x107 | ||
51 | #define REG_PWR_CTRL6 0x110 | ||
52 | #define REG_PWR_CTRL7 0x112 | ||
53 | |||
54 | #define REG_RAM_HADDR_SET 0x200 | ||
55 | #define REG_RAM_VADDR_SET 0x201 | ||
56 | #define REG_RW_GRAM 0x202 | ||
57 | #define REG_RAM_HADDR_START 0x210 | ||
58 | #define REG_RAM_HADDR_END 0x211 | ||
59 | #define REG_RAM_VADDR_START 0x212 | ||
60 | #define REG_RAM_VADDR_END 0x213 | ||
61 | #define REG_RW_NVM 0x280 | ||
62 | #define REG_VCOM_HVOLTAGE1 0x281 | ||
63 | #define REG_VCOM_HVOLTAGE2 0x282 | ||
64 | |||
65 | #define REG_GAMMA_CTRL1 0x300 | ||
66 | #define REG_GAMMA_CTRL2 0x301 | ||
67 | #define REG_GAMMA_CTRL3 0x302 | ||
68 | #define REG_GAMMA_CTRL4 0x303 | ||
69 | #define REG_GAMMA_CTRL5 0x304 | ||
70 | #define REG_GAMMA_CTRL6 0x305 | ||
71 | #define REG_GAMMA_CTRL7 0x306 | ||
72 | #define REG_GAMMA_CTRL8 0x307 | ||
73 | #define REG_GAMMA_CTRL9 0x308 | ||
74 | #define REG_GAMMA_CTRL10 0x309 | ||
75 | #define REG_GAMMA_CTRL11 0x30A | ||
76 | #define REG_GAMMA_CTRL12 0x30B | ||
77 | #define REG_GAMMA_CTRL13 0x30C | ||
78 | #define REG_GAMMA_CTRL14 0x30D | ||
79 | |||
80 | #define REG_BIMG_NR_LINE 0x400 | ||
81 | #define REG_BIMG_DISP_CTRL 0x401 | ||
82 | #define REG_BIMG_VSCROLL_CTRL 0x404 | ||
83 | |||
84 | #define REG_PARTIMG1_POS 0x500 | ||
85 | #define REG_PARTIMG1_RAM_START 0x501 | ||
86 | #define REG_PARTIMG1_RAM_END 0x502 | ||
87 | #define REG_PARTIMG2_POS 0x503 | ||
88 | #define REG_PARTIMG2_RAM_START 0x504 | ||
89 | #define REG_PARTIMG2_RAM_END 0x505 | ||
90 | |||
91 | #define REG_SOFT_RESET 0x600 | ||
92 | #define REG_ENDIAN_CTRL 0x606 | ||
93 | #define REG_NVM_ACCESS_CTRL 0x6F0 | ||
94 | |||
95 | /* Bits */ | ||
96 | #define DRIVER_OUTPUT_SS_BIT (1 << 8) | ||
97 | #define DRIVER_OUTPUT_SM_BIT (1 << 10) | ||
98 | |||
99 | #define SOFT_RESET_EN (1 << 0) | ||
100 | #define SOFT_RESET_DIS (0 << 0) | ||
101 | |||
102 | #define ENDIAN_CTRL_BIG | ||
103 | #define ENDIAN_CTRL_LITTLE | ||
104 | |||
105 | #endif /* __R61509_H */ \ No newline at end of file | ||