diff options
| author | Dave Chapman <dave@dchapman.com> | 2009-07-16 00:12:46 +0000 |
|---|---|---|
| committer | Dave Chapman <dave@dchapman.com> | 2009-07-16 00:12:46 +0000 |
| commit | c969047feac408aea61539f5c5244a8ad588ad84 (patch) | |
| tree | ccacd3a944fa198928cdef1212aa2424d8776969 /firmware/export | |
| parent | 02f5a001fecf83d2ae16aa3231b28378442ebfd0 (diff) | |
| download | rockbox-c969047feac408aea61539f5c5244a8ad588ad84.tar.gz rockbox-c969047feac408aea61539f5c5244a8ad588ad84.zip | |
The S5L8701 has the LCD controller in a different place.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21896 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/s5l8700.h | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index e0b56c7534..0eceaef6cd 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
| @@ -493,17 +493,23 @@ | |||
| 493 | #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ | 493 | #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ |
| 494 | 494 | ||
| 495 | /* 26. LCD INTERFACE CONTROLLER */ | 495 | /* 26. LCD INTERFACE CONTROLLER */ |
| 496 | #define LCD_CON (*(REG32_PTR_T)(0x3C100000)) /* Control register. */ | 496 | #ifdef CPU_S5L8700 |
| 497 | #define LCD_WCMD (*(REG32_PTR_T)(0x3C100004)) /* Write command register. */ | 497 | #define LCD_BASE 0x3C100000 |
| 498 | #define LCD_RCMD (*(REG32_PTR_T)(0x3C10000C)) /* Read command register. */ | 498 | #else /* CPU_S5L8701 */ |
| 499 | #define LCD_RDATA (*(REG32_PTR_T)(0x3C100010)) /* Read data register. */ | 499 | #define LCD_BASE 0x38600000 |
| 500 | #define LCD_DBUFF (*(REG32_PTR_T)(0x3C100014)) /* Read Data buffer */ | 500 | #endif |
| 501 | #define LCD_INTCON (*(REG32_PTR_T)(0x3C100018)) /* Interrupt control register */ | 501 | |
| 502 | #define LCD_STATUS (*(REG32_PTR_T)(0x3C10001C)) /* LCD Interface status 0106 */ | 502 | #define LCD_CON (*(REG16_PTR_T)(LCD_BASE+0x00)) /* Control register. */ |
| 503 | #define LCD_PHTIME (*(REG32_PTR_T)(0x3C100020)) /* Phase time register 0060 */ | 503 | #define LCD_WCMD (*(REG16_PTR_T)(LCD_BASE+0x04)) /* Write command register. */ |
| 504 | #define LCD_RST_TIME (*(REG32_PTR_T)(0x3C100024)) /* Reset active period 07FF */ | 504 | #define LCD_RCMD (*(REG16_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */ |
| 505 | #define LCD_DRV_RST (*(REG32_PTR_T)(0x3C100028)) /* Reset drive signal */ | 505 | #define LCD_RDATA (*(REG16_PTR_T)(LCD_BASE+0x10)) /* Read data register. */ |
| 506 | #define LCD_WDATA (*(REG32_PTR_T)(0x3C100040)) /* Write data register FIXME */ | 506 | #define LCD_DBUFF (*(REG16_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */ |
| 507 | #define LCD_INTCON (*(REG16_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */ | ||
| 508 | #define LCD_STATUS (*(REG16_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */ | ||
| 509 | #define LCD_PHTIME (*(REG16_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */ | ||
| 510 | #define LCD_RST_TIME (*(REG16_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */ | ||
| 511 | #define LCD_DRV_RST (*(REG16_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */ | ||
| 512 | #define LCD_WDATA (*(REG16_PTR_T)(LCD_BASE+0x40)) /* Write data register FIXME */ | ||
| 507 | 513 | ||
| 508 | /* 27. CLCD CONTROLLER */ | 514 | /* 27. CLCD CONTROLLER */ |
| 509 | #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ | 515 | #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ |