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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-04-18 17:38:55 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-04-18 17:38:55 +0000 |
commit | a54e0b6dba1b79b6a449395ffdbfc7220bbbe80c (patch) | |
tree | 85a199fd647b060caf8605cd991200f14a3cece8 /firmware/export | |
parent | 14a510aff28c5e5a7417f6ee39377d7ae947635d (diff) | |
download | rockbox-a54e0b6dba1b79b6a449395ffdbfc7220bbbe80c.tar.gz rockbox-a54e0b6dba1b79b6a449395ffdbfc7220bbbe80c.zip |
Onda VX747:
* Add YUV support
* Clean up LCD driver a bit and speed it up
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20730 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/jz4740.h | 102 | ||||
-rw-r--r-- | firmware/export/r61509.h | 1 |
2 files changed, 79 insertions, 24 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index cacdd1e488..b0f3f538a3 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h | |||
@@ -1305,10 +1305,10 @@ | |||
1305 | #define ICDC_CDCCR1_SUSPD (1 << 1) | 1305 | #define ICDC_CDCCR1_SUSPD (1 << 1) |
1306 | #define ICDC_CDCCR1_RST (1 << 0) | 1306 | #define ICDC_CDCCR1_RST (1 << 0) |
1307 | 1307 | ||
1308 | #define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16) | 1308 | #define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16) |
1309 | #define ICDC_CDCCR2_SMPR(n) ((n & 4) << 8) | 1309 | #define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8) |
1310 | #define ICDC_CDCCR2_MICBG(n) ((n & 2) << 4) | 1310 | #define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4) |
1311 | #define ICDC_CDCCR2_HPVOL(n) ((n & 2) << 0) | 1311 | #define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0) |
1312 | 1312 | ||
1313 | #define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5) | 1313 | #define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5) |
1314 | 1314 | ||
@@ -1423,7 +1423,7 @@ | |||
1423 | #define SSI_CR1_MULTS (1 << 22) | 1423 | #define SSI_CR1_MULTS (1 << 22) |
1424 | #define SSI_CR1_FMAT_BIT 20 | 1424 | #define SSI_CR1_FMAT_BIT 20 |
1425 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) | 1425 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
1426 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ | 1426 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ |
1427 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ | 1427 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
1428 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ | 1428 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
1429 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ | 1429 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
@@ -4984,7 +4984,7 @@ do{ \ | |||
4984 | 4984 | ||
4985 | // IPU_REG_BASE | 4985 | // IPU_REG_BASE |
4986 | #define IPU_P_BASE 0x13080000 | 4986 | #define IPU_P_BASE 0x13080000 |
4987 | #define IPU__OFFSET 0x13080000 | 4987 | #define IPU_V_BASE 0xB3080000 |
4988 | #define IPU__SIZE 0x00001000 | 4988 | #define IPU__SIZE 0x00001000 |
4989 | 4989 | ||
4990 | struct ipu_module | 4990 | struct ipu_module |
@@ -5069,10 +5069,12 @@ struct Ration2m | |||
5069 | #define INFMT_YCbCr422 (5 << 0) | 5069 | #define INFMT_YCbCr422 (5 << 0) |
5070 | #define INFMT_YCbCr444 (6 << 0) | 5070 | #define INFMT_YCbCr444 (6 << 0) |
5071 | #define INFMT_YCbCr411 (7 << 0) | 5071 | #define INFMT_YCbCr411 (7 << 0) |
5072 | #define INFMT_MASK (7) | ||
5072 | 5073 | ||
5073 | #define OUTFMT_RGB555 (0 << 16) | 5074 | #define OUTFMT_RGB555 (0 << 16) |
5074 | #define OUTFMT_RGB565 (1 << 16) | 5075 | #define OUTFMT_RGB565 (1 << 16) |
5075 | #define OUTFMT_RGB888 (2 << 16) | 5076 | #define OUTFMT_RGB888 (2 << 16) |
5077 | #define OUTFMT_MASK (3 << 16) | ||
5076 | 5078 | ||
5077 | // REG_IN_FM_GS field define | 5079 | // REG_IN_FM_GS field define |
5078 | #define IN_FM_W(val) ((val) << 16) | 5080 | #define IN_FM_W(val) ((val) << 16) |
@@ -5086,7 +5088,6 @@ struct Ration2m | |||
5086 | #define U_STRIDE(val) ((val) << 16) | 5088 | #define U_STRIDE(val) ((val) << 16) |
5087 | #define V_STRIDE(val) ((val) << 0) | 5089 | #define V_STRIDE(val) ((val) << 0) |
5088 | 5090 | ||
5089 | |||
5090 | #define VE_IDX_SFT 0 | 5091 | #define VE_IDX_SFT 0 |
5091 | #define HE_IDX_SFT 16 | 5092 | #define HE_IDX_SFT 16 |
5092 | 5093 | ||
@@ -5099,53 +5100,106 @@ struct Ration2m | |||
5099 | #define W_COEF_MSK 0xFF | 5100 | #define W_COEF_MSK 0xFF |
5100 | 5101 | ||
5101 | // function about REG_CTRL | 5102 | // function about REG_CTRL |
5102 | #define IPU_STOP_IPU(IPU_V_BASE) \ | 5103 | #define IPU_STOP_IPU() \ |
5103 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; | 5104 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; |
5104 | 5105 | ||
5105 | #define IPU_RUN_IPU(IPU_V_BASE) \ | 5106 | #define IPU_RUN_IPU() \ |
5106 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; | 5107 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; |
5107 | 5108 | ||
5108 | #define IPU_RESET_IPU(IPU_V_BASE) \ | 5109 | #define IPU_RESET_IPU() \ |
5109 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; | 5110 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; |
5110 | 5111 | ||
5111 | #define IPU_DISABLE_IRQ(IPU_V_BASE) \ | 5112 | #define IPU_DISABLE_IRQ() \ |
5112 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; | 5113 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; |
5113 | 5114 | ||
5114 | #define IPU_DISABLE_RSIZE(IPU_V_BASE) \ | 5115 | #define IPU_DISABLE_RSIZE() \ |
5115 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; | 5116 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; |
5116 | 5117 | ||
5117 | #define IPU_ENABLE_RSIZE(IPU_V_BASE) \ | 5118 | #define IPU_ENABLE_RSIZE() \ |
5118 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; | 5119 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; |
5119 | 5120 | ||
5120 | #define IPU_IS_ENABLED(IPU_V_BASE) \ | 5121 | #define IPU_IS_ENABLED() \ |
5121 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) | 5122 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) |
5122 | 5123 | ||
5123 | // function about REG_STATUS | 5124 | // function about REG_STATUS |
5124 | #define IPU_CLEAR_END_FLAG(IPU_V_BASE) \ | 5125 | #define IPU_CLEAR_END_FLAG() \ |
5125 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; | 5126 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; |
5126 | 5127 | ||
5127 | #define IPU_POLLING_END_FLAG(IPU_V_BASE) \ | 5128 | #define IPU_POLLING_END_FLAG() \ |
5128 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) | 5129 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) |
5129 | 5130 | ||
5131 | #define IPU_SET_INFMT(fmt) \ | ||
5132 | REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt); | ||
5133 | |||
5134 | #define IPU_SET_OUTFMT(fmt) \ | ||
5135 | REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt); | ||
5136 | |||
5137 | #define IPU_SET_IN_FM(w, h) \ | ||
5138 | REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h); | ||
5139 | |||
5140 | #define IPU_SET_Y_STRIDE(stride) \ | ||
5141 | REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride); | ||
5142 | |||
5143 | #define IPU_SET_UV_STRIDE(u, v) \ | ||
5144 | REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v); | ||
5145 | |||
5146 | #define IPU_SET_Y_ADDR(addr) \ | ||
5147 | REG32(IPU_V_BASE + REG_Y_ADDR) = (addr); | ||
5148 | |||
5149 | #define IPU_SET_U_ADDR(addr) \ | ||
5150 | REG32(IPU_V_BASE + REG_U_ADDR) = (addr); | ||
5151 | |||
5152 | #define IPU_SET_V_ADDR(addr) \ | ||
5153 | REG32(IPU_V_BASE + REG_V_ADDR) = (addr); | ||
5154 | |||
5155 | #define IPU_SET_OUT_ADDR(addr) \ | ||
5156 | REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr); | ||
5157 | |||
5158 | #define IPU_SET_OUT_FM(w, h) \ | ||
5159 | REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h); | ||
5160 | |||
5161 | #define IPU_SET_OUT_STRIDE(stride) \ | ||
5162 | REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride); | ||
5163 | |||
5164 | #define IPU_SET_CSC_C0_COEF(coef) \ | ||
5165 | REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef); | ||
5166 | |||
5167 | #define IPU_SET_CSC_C1_COEF(coef) \ | ||
5168 | REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef); | ||
5169 | |||
5170 | #define IPU_SET_CSC_C2_COEF(coef) \ | ||
5171 | REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef); | ||
5172 | |||
5173 | #define IPU_SET_CSC_C3_COEF(coef) \ | ||
5174 | REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef); | ||
5175 | |||
5176 | #define IPU_SET_CSC_C4_COEF(coef) \ | ||
5177 | REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef); | ||
5178 | |||
5179 | /* YCbCr */ | ||
5130 | /* parameter | 5180 | /* parameter |
5131 | R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1} | 5181 | R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1} |
5132 | G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3} | 5182 | G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3} |
5133 | B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4} | 5183 | B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4} |
5134 | */ | 5184 | */ |
5185 | #define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */ | ||
5186 | #define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */ | ||
5187 | #define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */ | ||
5188 | #define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */ | ||
5189 | #define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */ | ||
5135 | 5190 | ||
5136 | #if 1 | 5191 | |
5137 | #define YUV_CSC_C0 0x4A8 /* 1.164 * 1024 */ | 5192 | /* YUV */ |
5138 | #define YUV_CSC_C1 0x662 /* 1.596 * 1024 */ | 5193 | /* parameter |
5139 | #define YUV_CSC_C2 0x191 /* 0.392 * 1024 */ | 5194 | R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1} |
5140 | #define YUV_CSC_C3 0x341 /* 0.813 * 1024 */ | 5195 | G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3} |
5141 | #define YUV_CSC_C4 0x811 /* 2.017 * 1024 */ | 5196 | B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4} |
5142 | #else | 5197 | */ |
5143 | #define YUV_CSC_C0 0x400 | 5198 | #define YUV_CSC_C0 0x400 |
5144 | #define YUV_CSC_C1 0x59C | 5199 | #define YUV_CSC_C1 0x59C |
5145 | #define YUV_CSC_C2 0x161 | 5200 | #define YUV_CSC_C2 0x161 |
5146 | #define YUV_CSC_C3 0x2DC | 5201 | #define YUV_CSC_C3 0x2DC |
5147 | #define YUV_CSC_C4 0x718 | 5202 | #define YUV_CSC_C4 0x718 |
5148 | #endif | ||
5149 | 5203 | ||
5150 | #endif /* _IPU_H_ */ | 5204 | #endif /* _IPU_H_ */ |
5151 | 5205 | ||
diff --git a/firmware/export/r61509.h b/firmware/export/r61509.h index 53f0440742..f61b620084 100644 --- a/firmware/export/r61509.h +++ b/firmware/export/r61509.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define __R61509_H | 26 | #define __R61509_H |
27 | 27 | ||
28 | /* Register list */ | 28 | /* Register list */ |
29 | #define REG_DEVICE_CODE 0x000 | ||
29 | #define REG_DRIVER_OUTPUT 0x001 | 30 | #define REG_DRIVER_OUTPUT 0x001 |
30 | #define REG_LCD_DR_WAVE_CTRL 0x002 | 31 | #define REG_LCD_DR_WAVE_CTRL 0x002 |
31 | #define REG_ENTRY_MODE 0x003 | 32 | #define REG_ENTRY_MODE 0x003 |