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authorMarcin Bukat <marcin.bukat@gmail.com>2011-05-30 21:10:37 +0000
committerMarcin Bukat <marcin.bukat@gmail.com>2011-05-30 21:10:37 +0000
commit976a1699da373f01dabc9353b34aef261ebf740f (patch)
tree5f1649ceb51d603471e6b1cf5dcb5192626897d6 /firmware/export
parent8a5a2b82fd2d35e3eb7afa8f0dc875e3874988bb (diff)
downloadrockbox-976a1699da373f01dabc9353b34aef261ebf740f.tar.gz
rockbox-976a1699da373f01dabc9353b34aef261ebf740f.zip
Rockchip rk27xx port initial commit. This is still work in progress.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29935 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r--firmware/export/config.h13
-rw-r--r--firmware/export/config/rk27generic.h175
-rw-r--r--firmware/export/cpu.h3
-rw-r--r--firmware/export/i2c-rk27xx.h32
-rw-r--r--firmware/export/rk27xx.h1022
5 files changed, 1242 insertions, 3 deletions
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 003f68335a..2c7c6e89db 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -75,6 +75,7 @@
75#define AT91SAM9260 9260 75#define AT91SAM9260 9260
76#define AS3525v2 35252 76#define AS3525v2 35252
77#define IMX233 233 77#define IMX233 233
78#define RK27XX 2700
78 79
79/* platforms 80/* platforms
80 * bit fields to allow PLATFORM_HOSTED to be OR'ed e.g. with a 81 * bit fields to allow PLATFORM_HOSTED to be OR'ed e.g. with a
@@ -222,6 +223,7 @@
222#define LCD_VIBE500 39 /* as used by the Packard Bell Vibe 500 */ 223#define LCD_VIBE500 39 /* as used by the Packard Bell Vibe 500 */
223#define LCD_IPOD6G 40 /* as used by the iPod Nano 2nd Generation */ 224#define LCD_IPOD6G 40 /* as used by the iPod Nano 2nd Generation */
224#define LCD_FUZEPLUS 41 225#define LCD_FUZEPLUS 41
226#define LCD_SPFD5420A 42 /* rk27xx */
225 227
226/* LCD_PIXELFORMAT */ 228/* LCD_PIXELFORMAT */
227#define HORIZONTAL_PACKING 1 229#define HORIZONTAL_PACKING 1
@@ -260,6 +262,7 @@ Lyre prototype 1 */
260#define I2C_AS3525 15 262#define I2C_AS3525 15
261#define I2C_S5L8702 16 /* Same as S5L8700, but with two channels */ 263#define I2C_S5L8702 16 /* Same as S5L8700, but with two channels */
262#define I2C_IMX233 17 264#define I2C_IMX233 17
265#define I2C_RK27XX 18
263 266
264/* CONFIG_LED */ 267/* CONFIG_LED */
265#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ 268#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
@@ -271,6 +274,7 @@ Lyre prototype 1 */
271#define NAND_TCC 2 274#define NAND_TCC 2
272#define NAND_SAMSUNG 3 275#define NAND_SAMSUNG 3
273#define NAND_CC 4 /* ChinaChip */ 276#define NAND_CC 4 /* ChinaChip */
277#define NAND_RK27XX 5
274 278
275/* CONFIG_RTC */ 279/* CONFIG_RTC */
276#define RTC_M41ST84W 1 /* Archos Recorder */ 280#define RTC_M41ST84W 1 /* Archos Recorder */
@@ -448,6 +452,8 @@ Lyre prototype 1 */
448#include "config/mpiohd200.h" 452#include "config/mpiohd200.h"
449#elif defined(MPIO_HD300) 453#elif defined(MPIO_HD300)
450#include "config/mpiohd300.h" 454#include "config/mpiohd300.h"
455#elif defined(RK27_GENERIC)
456#include "config/rk27generic.h"
451#elif defined(SDLAPP) 457#elif defined(SDLAPP)
452#include "config/sdlapp.h" 458#include "config/sdlapp.h"
453#elif defined(ANDROID) 459#elif defined(ANDROID)
@@ -533,8 +539,8 @@ Lyre prototype 1 */
533 539
534#elif defined(CPU_TCC77X) || defined(CPU_TCC780X) || (CONFIG_CPU == DM320) \ 540#elif defined(CPU_TCC77X) || defined(CPU_TCC780X) || (CONFIG_CPU == DM320) \
535 || (CONFIG_CPU == AT91SAM9260) || (CONFIG_CPU == AS3525v2) \ 541 || (CONFIG_CPU == AT91SAM9260) || (CONFIG_CPU == AS3525v2) \
536 || (CONFIG_CPU == S5L8702) || (CONFIG_PLATFORM & PLATFORM_ANDROID) \ 542 || (CONFIG_CPU == S5L8702) || (CONFIG_CPU == IMX233) \
537 || (CONFIG_CPU == IMX233) 543 || (CONFIG_CPU == RK27XX) ||(CONFIG_PLATFORM & PLATFORM_ANDROID)
538#define CPU_ARM 544#define CPU_ARM
539#define ARM_ARCH 5 /* ARMv5 */ 545#define ARM_ARCH 5 /* ARMv5 */
540 546
@@ -774,7 +780,8 @@ Lyre prototype 1 */
774#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) \ 780#if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) \
775 || (CONFIG_CPU == AS3525) || (CONFIG_CPU == AS3525v2) \ 781 || (CONFIG_CPU == AS3525) || (CONFIG_CPU == AS3525v2) \
776 || defined(CPU_S5L870X) || (CONFIG_CPU == S3C2440) \ 782 || defined(CPU_S5L870X) || (CONFIG_CPU == S3C2440) \
777 || defined(APPLICATION) || (CONFIG_CPU == PP5002) 783 || defined(APPLICATION) || (CONFIG_CPU == PP5002) \
784 || (CONFIG_CPU == RK27XX)
778#define HAVE_SEMAPHORE_OBJECTS 785#define HAVE_SEMAPHORE_OBJECTS
779#endif 786#endif
780 787
diff --git a/firmware/export/config/rk27generic.h b/firmware/export/config/rk27generic.h
new file mode 100644
index 0000000000..5427d1fed4
--- /dev/null
+++ b/firmware/export/config/rk27generic.h
@@ -0,0 +1,175 @@
1/*
2 * This config file is for Rockchip rk27xx reference design
3 */
4#define TARGET_TREE /* this target is using the target tree system */
5
6/* For Rolo and boot loader */
7#define MODEL_NUMBER 78
8
9#define MODEL_NAME "Rockchip 27xx generic"
10
11/* define this if you have recording possibility */
12/* #define HAVE_RECORDING */
13
14/* Define bitmask of input sources - recordable bitmask can be defined
15 explicitly if different */
16#define INPUT_SRC_CAPS (SRC_CAP_LINEIN)
17
18/* define the bitmask of hardware sample rates */
19#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
20 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
21 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
22
23/* define the bitmask of recording sample rates */
24#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
25 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
26 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
27
28/* define this if you have a bitmap LCD display */
29#define HAVE_LCD_BITMAP
30
31/* define this if you can flip your LCD */
32/* #define HAVE_LCD_FLIP */
33
34/* define this if you have a colour LCD */
35#define HAVE_LCD_COLOR
36
37/* define this if you want album art for this target */
38#define HAVE_ALBUMART
39
40/* define this to enable bitmap scaling */
41#define HAVE_BMP_SCALING
42
43/* define this to enable JPEG decoding */
44#define HAVE_JPEG
45
46/* define this if you can invert the colours on your LCD */
47/* #define HAVE_LCD_INVERT */
48
49/* define this if you have access to the quickscreen */
50#define HAVE_QUICKSCREEN
51
52/* define this if you have access to the pitchscreen */
53#define HAVE_PITCHSCREEN
54
55/* define this if you would like tagcache to build on this target */
56#define HAVE_TAGCACHE
57
58/* define this if you have a flash memory storage */
59#define HAVE_FLASH_STORAGE
60
61#define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND)
62
63#define CONFIG_NAND NAND_RK27XX
64
65/* commented for now */
66/* #define HAVE_HOTSWAP */
67
68#define NUM_DRIVES 2
69#define SECTOR_SIZE 512
70
71/* for small(ish) SD cards */
72#define HAVE_FAT16SUPPORT
73
74/* LCD dimensions */
75#define LCD_WIDTH 400
76#define LCD_HEIGHT 240
77#define LCD_DEPTH 16 /* pseudo 262.144 colors */
78#define LCD_PIXELFORMAT RGB565 /* rgb565 */
79
80/* Define this if the LCD can shut down */
81/* #define HAVE_LCD_SHUTDOWN */
82
83/* Define this if your LCD can be enabled/disabled */
84/* #define HAVE_LCD_ENABLE */
85
86/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
87 should be defined as well. */
88#ifndef BOOTLOADER
89/* TODO: #define HAVE_LCD_SLEEP */
90/* TODO: #define HAVE_LCD_SLEEP_SETTING */
91#endif
92
93#define CONFIG_KEYPAD IPOD_4G_PAD
94
95/* Define this to enable morse code input */
96#define HAVE_MORSE_INPUT
97
98/* Define this if you do software codec */
99#define CONFIG_CODEC SWCODEC
100
101/* define this if you have a real-time clock */
102/* #define CONFIG_RTC RTC_NANO2G */
103
104/* Define if the device can wake from an RTC alarm */
105/* #define HAVE_RTC_ALARM */
106
107#define CONFIG_LCD LCD_SPFD5420A
108
109/* Define the type of audio codec */
110/* #define HAVE_RK27XX_CODEC */
111
112/* #define HAVE_PCM_DMA_ADDRESS */
113
114/* Define this for LCD backlight available */
115#define HAVE_BACKLIGHT
116
117/* Doesn't work so comment it out for now */
118/* #define HAVE_BACKLIGHT_BRIGHTNESS */
119
120/* Define this if you have a software controlled poweroff */
121#define HAVE_SW_POWEROFF
122
123/* The number of bytes reserved for loadable codecs */
124#define CODEC_SIZE 0x100000
125
126/* The number of bytes reserved for loadable plugins */
127#define PLUGIN_BUFFER_SIZE 0x80000
128
129/* TODO: Figure out real values */
130#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
131#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
132#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
133#define BATTERY_CAPACITY_INC 10 /* capacity increment */
134#define BATTERY_TYPES_COUNT 1 /* only one type */
135
136/* Hardware controlled charging with monitoring */
137#define CONFIG_CHARGING CHARGING_MONITOR
138
139/* define current usage levels */
140/* TODO: #define CURRENT_NORMAL
141 * TODO: #define CURRENT_BACKLIGHT 23
142 */
143
144/* define this if the unit can be powered or charged via USB */
145#define HAVE_USB_POWER
146
147/* Define this if your LCD can set contrast */
148/* #define HAVE_LCD_CONTRAST */
149
150/* The exact type of CPU */
151#define CONFIG_CPU RK27XX
152
153/* I2C interface */
154#define CONFIG_I2C I2C_RK27XX
155
156/* Define this to the CPU frequency */
157#define CPU_FREQ 200000000
158
159/* define this if the hardware can be powered off while charging */
160#define HAVE_POWEROFF_WHILE_CHARGING
161
162/* Offset ( in the firmware file's header ) to the file CRC */
163#define FIRMWARE_OFFSET_FILE_CRC 0
164
165/* Offset ( in the firmware file's header ) to the real data */
166#define FIRMWARE_OFFSET_FILE_DATA 8
167
168#define STORAGE_NEEDS_ALIGN
169
170/* Define this if you have adjustable CPU frequency */
171/* #define HAVE_ADJUSTABLE_CPU_FREQ */
172
173#define BOOTFILE_EXT "rk27"
174#define BOOTFILE "rockbox." BOOTFILE_EXT
175#define BOOTDIR "/.rockbox"
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index 777e36f62d..7405319822 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -77,3 +77,6 @@
77#if CONFIG_CPU == IMX233 77#if CONFIG_CPU == IMX233
78#include "imx233.h" 78#include "imx233.h"
79#endif 79#endif
80#if CONFIG_CPU == RK27XX
81#include "rk27xx.h"
82#endif
diff --git a/firmware/export/i2c-rk27xx.h b/firmware/export/i2c-rk27xx.h
new file mode 100644
index 0000000000..96baf566a7
--- /dev/null
+++ b/firmware/export/i2c-rk27xx.h
@@ -0,0 +1,32 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Bertrik Sikken
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#ifndef _I2C_RK27XX_H
23#define _I2C_RK27XX_H
24
25#include "config.h"
26
27void i2c_init(void);
28int i2c_write(unsigned char slave, int address, int len, const unsigned char *data);
29int i2c_read(unsigned char slave, int address, int len, unsigned char *data);
30
31#endif /* _I2C_RK27XX_H */
32
diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h
new file mode 100644
index 0000000000..a5cd396a33
--- /dev/null
+++ b/firmware/export/rk27xx.h
@@ -0,0 +1,1022 @@
1/* ARM part only for now */
2#define AHB_SRAM 0x00000000
3
4#define ARM_BUS0_BASE 0x18000000
5#define ARM_BUS1_BASE 0x18400000
6
7#define FLASH_BANK0 0x10000000
8#define FLASH_BANK1 0x11000000
9
10/* Timers */
11#define APB0_TIMER (ARM_BUS0_BASE + 0x00000000)
12#define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00))
13#define TMR0CVR (*(volatile unsigned long *)(APB0_TIMER + 0x04))
14#define TMR0CON (*(volatile unsigned long *)(APB0_TIMER + 0x08))
15
16#define TMR1LR (*(volatile unsigned long *)(APB0_TIMER + 0x10))
17#define TMR1CVR (*(volatile unsigned long *)(APB0_TIMER + 0x14))
18#define TMR1CON (*(volatile unsigned long *)(APB0_TIMER + 0x18))
19
20#define TMR2LR (*(volatile unsigned long *)(APB0_TIMER + 0x20))
21#define TMR2CVR (*(volatile unsigned long *)(APB0_TIMER + 0x24))
22#define TMR2CON (*(volatile unsigned long *)(APB0_TIMER + 0x28))
23
24/* UART0 */
25#define APB0_UART0 (ARM_BUS0_BASE + 0x00004000)
26#define UART0_RBR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
27#define UART0_THR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
28#define UART0_DLL (*(volatile unsigned long *)(APB0_UART0 + 0x00))
29#define UART0_DLH (*(volatile unsigned long *)(APB0_UART0 + 0x04))
30#define UART0_IER (*(volatile unsigned long *)(APB0_UART0 + 0x04))
31#define UART0_IIR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
32#define UART0_FCR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
33#define UART0_LCR (*(volatile unsigned long *)(APB0_UART0 + 0x0C))
34#define UART0_MCR (*(volatile unsigned long *)(APB0_UART0 + 0x10))
35#define UART0_LSR (*(volatile unsigned long *)(APB0_UART0 + 0x14))
36#define UART0_MSR (*(volatile unsigned long *)(APB0_UART0 + 0x18))
37
38/* UART1 */
39#define APB0_UART1 (ARM_BUS0_BASE + 0x00008000)
40#define UART1_RBR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
41#define UART1_THR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
42#define UART1_DLL (*(volatile unsigned long *)(APB0_UART1 + 0x00))
43#define UART1_DLH (*(volatile unsigned long *)(APB0_UART1 + 0x04))
44#define UART1_IER (*(volatile unsigned long *)(APB0_UART1 + 0x04))
45#define UART1_IIR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
46#define UART1_FCR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
47#define UART1_LCR (*(volatile unsigned long *)(APB0_UART1 + 0x0C))
48#define UART1_MCR (*(volatile unsigned long *)(APB0_UART1 + 0x10))
49#define UART1_LSR (*(volatile unsigned long *)(APB0_UART1 + 0x14))
50#define UART1_MSR (*(volatile unsigned long *)(APB0_UART1 + 0x18))
51
52/* GPIO ports A,B,C,D */
53#define APB0_GPIO0 (ARM_BUS0_BASE + 0x0000C000)
54#define GPIO_PADR (*(volatile unsigned long *)(APB0_GPIO0 + 0x00))
55#define GPIO_PACON (*(volatile unsigned long *)(APB0_GPIO0 + 0x04))
56#define GPIO_PBDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x08))
57#define GPIO_PBCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x0C))
58#define GPIO_PCDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x10))
59#define GPIO_PCCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x14))
60#define GPIO_PDDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x18))
61#define GPIO_PDCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x1C))
62#define GPIO_TEST (*(volatile unsigned long *)(APB0_GPIO0 + 0x20))
63#define GPIO_IEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x24))
64#define GPIO_IEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x28))
65#define GPIO_IEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x2C))
66#define GPIO_IED (*(volatile unsigned long *)(APB0_GPIO0 + 0x30))
67#define GPIO_ISA (*(volatile unsigned long *)(APB0_GPIO0 + 0x34))
68#define GPIO_ISB (*(volatile unsigned long *)(APB0_GPIO0 + 0x38))
69#define GPIO_ISC (*(volatile unsigned long *)(APB0_GPIO0 + 0x3C))
70#define GPIO_ISD (*(volatile unsigned long *)(APB0_GPIO0 + 0x40))
71#define GPIO_IBEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x44))
72#define GPIO_IBEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x48))
73#define GPIO_IBEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x4C))
74#define GPIO_IBED (*(volatile unsigned long *)(APB0_GPIO0 + 0x50))
75#define GPIO_IEVA (*(volatile unsigned long *)(APB0_GPIO0 + 0x54))
76#define GPIO_IEVB (*(volatile unsigned long *)(APB0_GPIO0 + 0x58))
77#define GPIO_IEVC (*(volatile unsigned long *)(APB0_GPIO0 + 0x5C))
78#define GPIO_IEVD (*(volatile unsigned long *)(APB0_GPIO0 + 0x60))
79#define GPIO_ICA (*(volatile unsigned long *)(APB0_GPIO0 + 0x64))
80#define GPIO_ICB (*(volatile unsigned long *)(APB0_GPIO0 + 0x68))
81#define GPIO_ICC (*(volatile unsigned long *)(APB0_GPIO0 + 0x6C))
82#define GPIO_ICD (*(volatile unsigned long *)(APB0_GPIO0 + 0x70))
83#define GPIO_ISR (*(volatile unsigned long *)(APB0_GPIO0 + 0x74))
84
85/* Watchdog */
86#define APB0_WDT (ARM_BUS0_BASE + 0x00010000)
87#define WDTLR (*(volatile unsigned long *)(APB0_WDT + 0x00))
88#define WDTCVR (*(volatile unsigned long *)(APB0_WDT + 0x04))
89#define WDTCON (*(volatile unsigned long *)(APB0_WDT + 0x08))
90
91/* RTC module documentation missing */
92#define APB0_RTC (ARM_BUS0_BASE + 0x00014000)
93#define RTC_TIME (*(volatile unsigned long *)(APB0_RTC + 0x00))
94#define RTC_DATE (*(volatile unsigned long *)(APB0_RTC + 0x04))
95#define RTC_TALARM (*(volatile unsigned long *)(APB0_RTC + 0x08))
96#define RTC_DALARM (*(volatile unsigned long *)(APB0_RTC + 0x0C))
97#define RTC_CTRL (*(volatile unsigned long *)(APB0_RTC + 0x10))
98#define RTC_RESET (*(volatile unsigned long *)(APB0_RTC + 0x14))
99#define RTC_PWOFF (*(volatile unsigned long *)(APB0_RTC + 0x18))
100#define RTC_PWFAIL (*(volatile unsigned long *)(APB0_RTC + 0x1C))
101
102/* SPI */
103#define APB0_SPI (ARM_BUS0_BASE + 0x00018000)
104#define SPI_TXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
105#define SPI_RXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
106#define SPI_IER (*(volatile unsigned long *)(APB0_SPI + 0x04))
107#define SPI_FCR (*(volatile unsigned long *)(APB0_SPI + 0x08))
108#define SPI_FWCR (*(volatile unsigned long *)(APB0_SPI + 0x0C))
109#define SPI_DLYCR (*(volatile unsigned long *)(APB0_SPI + 0x10))
110#define SPI_TXCR (*(volatile unsigned long *)(APB0_SPI + 0x14))
111#define SPI_RXCR (*(volatile unsigned long *)(APB0_SPI + 0x18))
112#define SPI_SSCR (*(volatile unsigned long *)(APB0_SPI + 0x1C))
113#define SPI_ISR (*(volatile unsigned long *)(APB0_SPI + 0x20))
114
115/* SCU module */
116#define APB0_SCU (ARM_BUS0_BASE + 0x0001C000)
117#define SCU_ID (*(volatile unsigned long *)(APB0_SCU + 0x00))
118#define SCU_REMAP (*(volatile unsigned long *)(APB0_SCU + 0x04))
119#define SCU_PLLCON1 (*(volatile unsigned long *)(APB0_SCU + 0x08))
120#define SCU_PLLCON2 (*(volatile unsigned long *)(APB0_SCU + 0x0C))
121#define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
122#define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
123#define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
124#define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
125#define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
126#define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))
127#define SCU_CHIPCFG (*(volatile unsigned long *)(APB0_SCU + 0x28))
128#define SCU_STATUS (*(volatile unsigned long *)(APB0_SCU + 0x2C))
129#define SCU_IOMUXA_CON (*(volatile unsigned long *)(APB0_SCU + 0x30))
130/* 20 - 31 reserved */
131#define IOMUX_I2S_PAD (1<<19)
132#define IOMUX_I2S_CODEC (0<<19)
133#define IOMUX_I2C_PAD (1<<18)
134#define IOMUX_I2C_CODEC (0<<18)
135#define IOMUX_GPIO_B7 (2<<16)
136#define IOMUX_NAND_CS3 (1<<16)
137#define IOMUX_I2C_SDA (0<<16)
138#define IOMUX_GPIO_B6 (2<<14)
139#define IOMUX_NAND_CS2 (1<<14)
140#define IOMUX_I2C_SCL (0<<14)
141#define IOMUX_SPI (2<<12)
142#define IOMUX_SD (1<<12)
143#define IOMUX_GPIO_B05 (0<<12)
144#define IOMUX_LCD_VSYNC (1<<11)
145#define IOMUX_GPIO_A7 (0<<11)
146#define IOMUX_LCD_DEN (1<<10)
147#define IOMUX_GPIO_A6 (0<<10)
148#define IOMUX_NAND_CS1 (1<<9)
149#define IOMUX_GPIO_A5 (0<<9)
150#define IOMUX_LCD_D22 (1<<8)
151#define IOMUX_GPIO_A4 (0<<8)
152#define IOMUX_UART0_NRTS (2<<6)
153#define IOMUX_LCD_D20 (1<<6)
154#define IOMUX_GPIO_A3 (0<<6)
155#define IOMUX_UART0_NCTS (2<<4)
156#define IOMUX_LCD_D18 (1<<4)
157#define IOMUX_GPIO_A2 (0<<4)
158#define IOMUX_UART0_TXD (2<<2)
159#define IOMUX_LCD_D17 (1<<2)
160#define IOMUX_GPIO_A1 (0<<2)
161#define IOMUX_UART0_RXD (2<<0)
162#define IOMUX_LCD_D16 (1<<0)
163#define IOMUX_GPIO_A0 (0<<0)
164
165#define SCU_IOMUXB_CON (*(volatile unsigned long *)(APB0_SCU + 0x34))
166/* bits 31 - 23 reserved */
167#define IOMUX_HADC (1<<22)
168#define IOMUX_VIP (0<<22)
169#define IOMUX_SDRAM_CKE (1<<21)
170#define IOMUX_GPIO_D3 (0<<21)
171#define IOMUX_UHC_VBUS (1<<20)
172#define IOMUX_GPIO_F4 (0<<20)
173#define IOMUX_UHC_OCUR (1<<19)
174#define IOMUX_GPIO_F3 (0<<19)
175#define IOMUX_GPIO_F2 (1<<18)
176#define IOMUX_SDRAM_A12 (0<<18)
177#define IOMUX_GPIO_F1 (1<<17)
178#define IOMUX_SDRAM_A11 (0<<17)
179#define IOMUX_VIP_CLK (1<<16)
180#define IOMUX_GPIO_F0 (0<<16)
181#define IOMUX_LCD_D815 (1<<15)
182#define IOMUX_GPIO_E07 (0<<15)
183#define IOMUX_PWM3 (1<<14)
184#define IOMUX_GPIO_D7 (0<<14)
185#define IOMUX_PWM2 (1<<13)
186#define IOMUX_GPIO_D6 (0<<13)
187#define IOMUX_PWM1 (1<<12)
188#define IOMUX_GPIO_D5 (0<<12)
189#define IOMUX_PWM0 (1<<11)
190#define IOMUX_GPIO_D4 (0<<11)
191#define IOMUX_SD_WPA (1<<10)
192#define IOMUX_GPIO_D2 (0<<10)
193#define IOMUX_UART1_RXD (2<<8)
194#define IOMUX_SD_CDA (1<<8)
195#define IOMUX_GPIO_D1 (0<<8)
196#define IOMUX_UART1_TXD (2<<6)
197#define IOMUX_SD_PCA (1<<6)
198#define IOMUX_GPIO_D0 (0<<6)
199#define IOMUX_STMEM_CS1 (1<<5)
200#define IOMUX_GPIO_C7 (0<<5)
201#define IOMUX_I2S_CLK (1<<4)
202#define IOMUX_GPIO_C6 (0<<4)
203#define IOMUX_I2S_SDO (1<<3)
204#define IOMUX_GPIO_C5 (0<<3)
205#define IOMUX_I2S_SDI (1<<2)
206#define IOMUX_GPIO_C4 (0<<2)
207#define IOMUX_I2S_LRCK (1<<1)
208#define IOMUX_GPIO_C3 (0<<1)
209#define IOMUX_I2S_SCLK (1<<0)
210#define IOMUX_GPIO_C2 (0<<0)
211
212#define SCU_GPIOUPCON (*(volatile unsigned long *)(APB0_SCU + 0x38))
213#define SCU_DIVCON2 (*(volatile unsigned long *)(APB0_SCU + 0x3C))
214
215/* I2C controller */
216#define APB0_I2C (ARM_BUS0_BASE + 0x00020000)
217#define I2C_MTXR (*(volatile unsigned long *)(APB0_I2C + 0x00))
218#define I2C_MRXR (*(volatile unsigned long *)(APB0_I2C + 0x04))
219#define I2C_STXR (*(volatile unsigned long *)(APB0_I2C + 0x08))
220#define I2C_SRXR (*(volatile unsigned long *)(APB0_I2C + 0x0C))
221#define I2C_SADDR (*(volatile unsigned long *)(APB0_I2C + 0x10))
222#define I2C_IER (*(volatile unsigned long *)(APB0_I2C + 0x14))
223#define I2C_ISR (*(volatile unsigned long *)(APB0_I2C + 0x18))
224#define I2C_LCMR (*(volatile unsigned long *)(APB0_I2C + 0x1C))
225#define I2C_LSR (*(volatile unsigned long *)(APB0_I2C + 0x20))
226#define I2C_CONR (*(volatile unsigned long *)(APB0_I2C + 0x24))
227#define I2C_OPR (*(volatile unsigned long *)(APB0_I2C + 0x28))
228
229/* SD card controller */
230#define APB0_SD (ARM_BUS0_BASE + 0x00024000)
231#define MMU_CTRL (*(volatile unsigned long *)(APB0_SD + 0x00))
232#define MMU_BIG_ENDIAN (1<<12)
233#define MMU_DMA_START (1<<11)
234#define MMU_DMA_WRITE (1<<10)
235#define MMU_MMU0_BUFI (0<<9)
236#define MMU_MMU0_BUFII (1<<9)
237#define MMU_CPU_BUFI (0<<8)
238#define MMU_CPU_BUFII (1<<8)
239#define MMU_BUFII_RESET (1<<7)
240#define MMU_BUFII_END (1<<6)
241#define MMU_BUFII_BYTE (0<<4)
242#define MMU_BUFII_HALFWORD (1<<4)
243#define MMU_BUFII_WORD (3<<4)
244#define MMU_BUFI_RESET (1<<3)
245#define MMU_BUFI_END (1<<2)
246#define MMU_BUFI_BYTE (0<<0)
247#define MMU_BUFI_HALFWORD (1<<0)
248#define MMU_BUFI_WORD (3<<0)
249
250#define MMU_PNRI (*(volatile unsigned long *)(APB0_SD + 0x04))
251#define CUR_PNRI (*(volatile unsigned long *)(APB0_SD + 0x08))
252#define MMU_PNRII (*(volatile unsigned long *)(APB0_SD + 0x0C))
253#define CUR_PNRII (*(volatile unsigned long *)(APB0_SD + 0x10))
254#define MMU_ADDR (*(volatile unsigned long *)(APB0_SD + 0x14))
255#define CUR_ADDR (*(volatile unsigned long *)(APB0_SD + 0x18))
256#define MMU_DATA (*(volatile unsigned long *)(APB0_SD + 0x1C))
257
258#define SD_CTRL (*(volatile unsigned long *)(APB0_SD + 0x20))
259#define SD_PWR_CD (1<<13)
260#define SD_PWR_CPU (0<<13)
261#define SD_DETECT_CDDAT3 (1<<12)
262#define SD_DETECT_MECH (0<<12)
263#define SD_CLOCK_DIS (1<<11)
264#define SD_CLOCK_EN (0<<11)
265#define SD_DIV(x) ((x)&0x7ff)
266
267#define SD_INT (*(volatile unsigned long *)(APB0_SD + 0x24))
268#define CMD_RES_STAT (1<<6)
269#define DATA_XFER_STAT (1<<5)
270#define CD_DETECT_STAT (1<<4)
271#define CMD_RES_INT_EN (1<<2)
272#define DATA_XFER_INT_EN (1<<1)
273#define CD_DETECT_IN_EN (1<<0)
274
275#define SD_CARD (*(volatile unsigned long *)(APB0_SD + 0x28))
276#define SD_CARD_SELECT (1<<7)
277#define SD_CARD_PWR_EN (1<<6)
278#define SD_CARD_DETECT_INT_EN (1<<5)
279#define SD_CARD_BSY (1<<2)
280#define SD_CARD_WRITE_PROTECT (1<<1)
281#define SD_CARD_DETECT (1<<0)
282
283#define SD_CMDREST (*(volatile unsigned long *)(APB0_SD + 0x30))
284#define CMD_XFER_START (1<<13)
285#define CMD_XFER_END (0<<13)
286#define RES_XFER_START (1<<12)
287#define RES_XFER_END (0<<12)
288#define RES_R1 (0<<9)
289#define RES_R1b (1<<9)
290#define RES_R2 (2<<9)
291#define RES_R3 (3<<9)
292#define RES_R6 (6<<9)
293#define CMD_RES_ERROR (1<<8)
294/* bits 0-5 cmd index */
295
296#define SD_CMDRES (*(volatile unsigned long *)(APB0_SD + 0x34))
297#define STAT_CMD_XFER_START (1<<8)
298#define STAT_RES_XFER_START (1<<7)
299#define STAT_CMD_RES_ERR (1<<6)
300#define STAT_CMD_RES_BUS_ERR (1<<5)
301#define STAT_RES_TIMEOUT_ERR (1<<4)
302#define STAT_RES_STARTBIT_ERR (1<<3)
303#define STAT_RES_INDEX_ERR (1<<2)
304#define STAT_RES_CRC_ERR (1<<1)
305#define STAT_RES_ENDBIT_ERR (1<<0)
306
307#define SD_DATAT (*(volatile unsigned long *)(APB0_SD + 0x3C))
308#define DATA_XFER_START (1<<13)
309#define DATA_XFER_WRITE (1<<12)
310#define DATA_XFER_READ (0<<12)
311#define DATA_BUS_4LINES (1<<11) /* rk2705/6/8 does not support this mode */
312#define DATA_BUS_1LINE (0<<11)
313#define DATA_XFER_DMA_EN (1<<10)
314#define DATA_XFER_DMA_DIS (0<<10)
315#define DATA_XFER_MULTI (1<<9)
316#define DATA_XFER_SINGLE (0<<9)
317#define DATA_XFER_ERR (1<<8)
318#define DATA_BUS_ERR (1<<7)
319#define DATA_TIMEOUT_ERR (1<<6)
320#define DATA_CRC_ERR (1<<5)
321#define READ_DAT_STARTBIT_ERR (1<<4)
322#define READ_DAT_ENDBIT_ERR (1<<3)
323#define WRITE_DAT_NOERR (2<<0)
324#define WRITE_DAT_CRC_ERR (5<<0)
325#define WRITE_DAT_NO_RES (7<<0)
326
327#define SD_CMD (*(volatile unsigned long *)(APB0_SD + 0x40))
328#define SD_RES3 (*(volatile unsigned long *)(APB0_SD + 0x44))
329#define SD_RES2 (*(volatile unsigned long *)(APB0_SD + 0x48))
330#define SD_RES1 (*(volatile unsigned long *)(APB0_SD + 0x4C))
331#define SD_RES0 (*(volatile unsigned long *)(APB0_SD + 0x50))
332
333/* I2S controller */
334#define APB0_I2S (ARM_BUS0_BASE + 0x00028000)
335#define I2S_OPR (*(volatile unsigned long *)(APB0_I2S + 0x00))
336#define I2S_TXR (*(volatile unsigned long *)(APB0_I2S + 0x04))
337#define I2S_RXR (*(volatile unsigned long *)(APB0_I2S + 0x08))
338#define I2S_TXCTL (*(volatile unsigned long *)(APB0_I2S + 0x0C))
339#define I2S_RXCTL (*(volatile unsigned long *)(APB0_I2S + 0x10))
340#define I2S_FIFOSTS (*(volatile unsigned long *)(APB0_I2S + 0x14))
341#define I2S_IER (*(volatile unsigned long *)(APB0_I2S + 0x18))
342#define I2S_ISR (*(volatile unsigned long *)(APB0_I2S + 0x1C))
343
344/* PWM timer */
345#define APB0_PWM (ARM_BUS0_BASE + 0x0002C000)
346#define PWMT0_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x00))
347#define PWMT0_HRC (*(volatile unsigned long *)(APB0_PWM + 0x04))
348#define PWMT0_LRC (*(volatile unsigned long *)(APB0_PWM + 0x08))
349#define PWMT0_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x0C))
350#define PWMT1_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x10))
351#define PWMT1_HRC (*(volatile unsigned long *)(APB0_PWM + 0x14))
352#define PWMT1_LRC (*(volatile unsigned long *)(APB0_PWM + 0x18))
353#define PWMT1_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x1C))
354#define PWMT2_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x20))
355#define PWMT2_HRC (*(volatile unsigned long *)(APB0_PWM + 0x24))
356#define PWMT2_LRC (*(volatile unsigned long *)(APB0_PWM + 0x28))
357#define PWMT2_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x2C))
358#define PWMT3_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x30))
359#define PWMT3_HRC (*(volatile unsigned long *)(APB0_PWM + 0x34))
360#define PWMT3_LRC (*(volatile unsigned long *)(APB0_PWM + 0x38))
361#define PWMT3_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x3C))
362
363/* ADC converter */
364#define APB0_ADC0 (ARM_BUS0_BASE + 0x00030000)
365#define ADC_DATA (*(volatile unsigned long *)(APB0_ADC0 + 0x00))
366#define ADC_STAT (*(volatile unsigned long *)(APB0_ADC0 + 0x04))
367#define ADC_CTRL (*(volatile unsigned long *)(APB0_ADC0 + 0x08))
368
369/* 0x18034000 - 0x18038000 reserved */
370
371/* GPIO ports E,F */
372#define APB0_GPIO1 (ARM_BUS0_BASE + 0x00038000)
373#define GPIO_PEDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x00))
374#define GPIO_PECON (*(volatile unsigned long *)(APB0_GPIO1 + 0x04))
375#define GPIO_PFDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x08))
376#define GPIO_PFCON (*(volatile unsigned long *)(APB0_GPIO1 + 0x0C))
377
378#define GPIO1_TEST (*(volatile unsigned long *)(APB0_GPIO1 + 0x20))
379#define GPIO_IEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x24))
380#define GPIO_IEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x28))
381
382#define GPIO_ISE (*(volatile unsigned long *)(APB0_GPIO1 + 0x34))
383#define GPIO_ISF (*(volatile unsigned long *)(APB0_GPIO1 + 0x38))
384
385#define GPIO_IBEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x44))
386#define GPIO_IBEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x48))
387
388#define GPIO_IEVE (*(volatile unsigned long *)(APB0_GPIO1 + 0x54))
389#define GPIO_IEVF (*(volatile unsigned long *)(APB0_GPIO1 + 0x58))
390
391#define GPIO_ICE (*(volatile unsigned long *)(APB0_GPIO1 + 0x64))
392#define GPIO_ICF (*(volatile unsigned long *)(APB0_GPIO1 + 0x68))
393
394#define GPIO1_ISR (*(volatile unsigned long *)(APB0_GPIO1 + 0x74))
395
396
397/* 0x1803C000 - 0x18080000 reserved */
398
399/* Interrupt controller */
400#define AHB0_INTC (ARM_BUS0_BASE + 0x00080000)
401#define INTC_SCR0 (*(volatile unsigned long *)(AHB0_INTC + 0x00))
402#define INTC_SCR1 (*(volatile unsigned long *)(AHB0_INTC + 0x04))
403#define INTC_SCR2 (*(volatile unsigned long *)(AHB0_INTC + 0x08))
404#define INTC_SCR3 (*(volatile unsigned long *)(AHB0_INTC + 0x0C))
405#define INTC_SCR4 (*(volatile unsigned long *)(AHB0_INTC + 0x10))
406#define INTC_SCR5 (*(volatile unsigned long *)(AHB0_INTC + 0x14))
407#define INTC_SCR6 (*(volatile unsigned long *)(AHB0_INTC + 0x18))
408#define INTC_SCR7 (*(volatile unsigned long *)(AHB0_INTC + 0x1C))
409#define INTC_SCR8 (*(volatile unsigned long *)(AHB0_INTC + 0x20))
410#define INTC_SCR9 (*(volatile unsigned long *)(AHB0_INTC + 0x24))
411#define INTC_SCR10 (*(volatile unsigned long *)(AHB0_INTC + 0x28))
412#define INTC_SCR11 (*(volatile unsigned long *)(AHB0_INTC + 0x2C))
413#define INTC_SCR12 (*(volatile unsigned long *)(AHB0_INTC + 0x30))
414#define INTC_SCR13 (*(volatile unsigned long *)(AHB0_INTC + 0x34))
415#define INTC_SCR14 (*(volatile unsigned long *)(AHB0_INTC + 0x38))
416#define INTC_SCR15 (*(volatile unsigned long *)(AHB0_INTC + 0x3C))
417#define INTC_SCR16 (*(volatile unsigned long *)(AHB0_INTC + 0x40))
418#define INTC_SCR17 (*(volatile unsigned long *)(AHB0_INTC + 0x44))
419#define INTC_SCR18 (*(volatile unsigned long *)(AHB0_INTC + 0x48))
420#define INTC_SCR19 (*(volatile unsigned long *)(AHB0_INTC + 0x4C))
421#define INTC_SCR20 (*(volatile unsigned long *)(AHB0_INTC + 0x50))
422#define INTC_SCR21 (*(volatile unsigned long *)(AHB0_INTC + 0x54))
423#define INTC_SCR22 (*(volatile unsigned long *)(AHB0_INTC + 0x58))
424#define INTC_SCR23 (*(volatile unsigned long *)(AHB0_INTC + 0x5C))
425#define INTC_SCR24 (*(volatile unsigned long *)(AHB0_INTC + 0x60))
426#define INTC_SCR25 (*(volatile unsigned long *)(AHB0_INTC + 0x64))
427#define INTC_SCR26 (*(volatile unsigned long *)(AHB0_INTC + 0x68))
428#define INTC_SCR27 (*(volatile unsigned long *)(AHB0_INTC + 0x6C))
429#define INTC_SCR28 (*(volatile unsigned long *)(AHB0_INTC + 0x70))
430#define INTC_SCR29 (*(volatile unsigned long *)(AHB0_INTC + 0x74))
431#define INTC_SCR30 (*(volatile unsigned long *)(AHB0_INTC + 0x78))
432#define INTC_SCR31 (*(volatile unsigned long *)(AHB0_INTC + 0x7C))
433
434#define INTC_ISR (*(volatile unsigned long *)(AHB0_INTC + 0x104))
435#define INTC_IPR (*(volatile unsigned long *)(AHB0_INTC + 0x108))
436#define INTC_IMR (*(volatile unsigned long *)(AHB0_INTC + 0x10C))
437
438#define INTC_IECR (*(volatile unsigned long *)(AHB0_INTC + 0x114))
439#define INTC_ICCR (*(volatile unsigned long *)(AHB0_INTC + 0x118))
440#define INTC_ISCR (*(volatile unsigned long *)(AHB0_INTC + 0x11C))
441
442#define INTC_TEST (*(volatile unsigned long *)(AHB0_INTC + 0x124))
443
444/* Bus arbiter module */
445#define AHB0_ARBITER (ARM_BUS0_BASE + 0x00084000)
446#define ARB_MODE (*(volatile unsigned long *)(AHB0_ARBITER + 0x00))
447#define ARB_PRIO1 (*(volatile unsigned long *)(AHB0_ARBITER + 0x04))
448#define ARB_PRIO2 (*(volatile unsigned long *)(AHB0_ARBITER + 0x08))
449#define ARB_PRIO3 (*(volatile unsigned long *)(AHB0_ARBITER + 0x0C))
450#define ARB_PRIO4 (*(volatile unsigned long *)(AHB0_ARBITER + 0x10))
451#define ARB_PRIO5 (*(volatile unsigned long *)(AHB0_ARBITER + 0x14))
452#define ARB_PRIO6 (*(volatile unsigned long *)(AHB0_ARBITER + 0x18))
453#define ARB_PRIO7 (*(volatile unsigned long *)(AHB0_ARBITER + 0x1C))
454#define ARB_PRIO8 (*(volatile unsigned long *)(AHB0_ARBITER + 0x20))
455#define ARB_PRIO9 (*(volatile unsigned long *)(AHB0_ARBITER + 0x24))
456#define ARB_PRIO10 (*(volatile unsigned long *)(AHB0_ARBITER + 0x28))
457#define ARB_PRIO11 (*(volatile unsigned long *)(AHB0_ARBITER + 0x2C))
458#define ARB_PRIO12 (*(volatile unsigned long *)(AHB0_ARBITER + 0x30))
459#define ARB_PRIO13 (*(volatile unsigned long *)(AHB0_ARBITER + 0x34))
460#define ARB_PRIO14 (*(volatile unsigned long *)(AHB0_ARBITER + 0x38))
461#define ARB_PRIO15 (*(volatile unsigned long *)(AHB0_ARBITER + 0x3C))
462
463/* Interprocessor communication module */
464#define AHB0_CPU_MAILBOX (ARM_BUS0_BASE + 0x00088000)
465#define MAILBOX_ID (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x00))
466#define H2C_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x10))
467#define H2C0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x20))
468#define H2C0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
469#define H2C1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x28))
470#define H2C1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x2C))
471#define H2C2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x30))
472#define H2C2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
473#define H2C3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x38))
474#define H2C3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x3C))
475
476#define C2H_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x40))
477#define C2H0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x50))
478#define C2H0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x54))
479#define C2H1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x58))
480#define C2H1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x5C))
481#define C2H2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x60))
482#define C2H2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x64))
483#define C2H3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x68))
484#define C2H3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x6C))
485
486/* Debug module */
487#define AHB0_CPU_DEBUGIF (ARM_BUS0_BASE + 0x0008C000)
488
489/* AHB DMA */
490#define AHB0_HDMA (ARM_BUS0_BASE + 0x00090000)
491#define HDMA_CON0 (*(volatile unsigned long *)(AHB0_HDMA + 0x00))
492#define HDMA_CON1 (*(volatile unsigned long *)(AHB0_HDMA + 0x04))
493#define HDMA_ISRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x08))
494#define HDMA_IDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x0C))
495#define HDMA_ICNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x10))
496#define HDMA_ISRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x14))
497#define HDMA_IDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x18))
498#define HDMA_ICNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x1C))
499#define HDMA_CSRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x20))
500#define HDMA_CDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x24))
501#define HDMA_CCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x28))
502#define HDMA_CSRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x2C))
503#define HDMA_CDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x30))
504#define HDMA_CCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x34))
505#define HDMA_ISR (*(volatile unsigned long *)(AHB0_HDMA + 0x38))
506#define HDMA_DSR (*(volatile unsigned long *)(AHB0_HDMA + 0x3C))
507#define HDMA_ISCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x40))
508#define HDMA_IPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x44))
509#define HDMA_IADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x48))
510#define HDMA_ISCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x4C))
511#define HDMA_IPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x50))
512#define HDMA_IADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x54))
513#define HDMA_CSCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x58))
514#define HDMA_CPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x5C))
515#define HDMA_CADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x60))
516#define HDMA_CSCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x64))
517#define HDMA_CPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x68))
518#define HDMA_CADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x6C))
519#define HDMA_PACNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x70))
520#define HDMA_PACNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x74))
521
522/* AHB-to-AHB bridge controller */
523#define AHB0_A2A_DMA (ARM_BUS0_BASE + 0x00094000)
524#define A2A_CON0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x00))
525#define A2A_ISRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x04))
526#define A2A_IDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x08))
527#define A2A_ICNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x0C))
528#define A2A_CSRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x10))
529#define A2A_CDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x14))
530#define A2A_CCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x18))
531#define A2A_CON1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x1C))
532#define A2A_ISRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x20))
533#define A2A_IDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x24))
534#define A2A_ICNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x28))
535#define A2A_CSRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x2C))
536#define A2A_CDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x30))
537#define A2A_CCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x34))
538#define A2A_INT_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x38))
539#define A2A_DMA_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x3C))
540#define A2A_ERR_ADR0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x40))
541#define A2A_ERR_OP0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x44))
542#define A2A_ERR_ADR1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x48))
543#define A2A_ERR_OP1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x4C))
544#define A2A_LCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x50))
545#define A2A_LCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x54))
546#define A2A_DOMAIN (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x58))
547
548/* 0x18098000 - 0x180A000 reserved */
549
550/* USB device controller */
551#define AHB0_UDC (ARM_BUS0_BASE + 0x000A0000)
552#define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00))
553#define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04))
554#define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08))
555
556#define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10))
557#define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14))
558#define EN_SOF_INTR (1<<0)
559#define EN_SETUP_INTR (1<<1)
560#define EN_IN0_INTR (1<<2)
561#define EN_OUT0_INTR (1<<3)
562#define EN_USBRST_INTR (1<<4)
563#define EN_RESUME_INTR (1<<5)
564#define EN_SUSP_INTR (1<<6)
565/* bit 7 reserved */
566#define EN_BOUT1_INTR (1<<8)
567#define EN_BIN2_INTR (1<<9)
568#define EN_IIN3_INTR (1<<10)
569#define EN_BOUT4_INTR (1<<11)
570#define EN_BIN5_INTR (1<<12)
571#define EN_IIN6_INTR (1<<13)
572#define EN_BOUT7_INTR (1<<14)
573#define EN_BIN8_INTR (1<<15)
574#define EN_IIN9_INTR (1<<16)
575#define EN_BOUT10_INTR (1<<17)
576#define EN_BIN11_INTR (1<<18)
577#define EN_IIN12_INTR (1<<19)
578#define EN_BOUT13_INTR (1<<20)
579#define EN_BIN14_INTR (1<<21)
580#define EN_IIN15_INTR (1<<22)
581/* bits 23-26 TEST */
582/* bits 27-31 reserved */
583
584#define INT2FLAG (*(volatile unsigned long *)(AHB0_UDC + 0x18))
585#define SOF_INTR (1<<0)
586#define SETUP_INTR (1<<1)
587#define IN0_INTR (1<<2)
588#define OUT0_INTR (1<<3)
589#define USBRST_INTR (1<<4)
590#define RESUME_INTR (1<<5)
591#define SUSP_INTR (1<<6)
592/* bit 7 reserved */
593#define BOUT1_INTR (1<<8)
594#define BIN2_INTR (1<<9)
595#define IIN3_INTR (1<<10)
596#define BOUT4_INTR (1<<11)
597#define BIN5_INTR (1<<12)
598#define IIN6_INTR (1<<13)
599#define BOUT7_INTR (1<<14)
600#define BIN8_INTR (1<<15)
601#define IIN9_INTR (1<<16)
602#define BOUT10_INTR (1<<17)
603#define BIN11_INTR (1<<18)
604#define IIN12_INTR (1<<19)
605#define BOUT13_INTR (1<<20)
606#define BIN14_INTR (1<<21)
607#define IIN15_INTR (1<<22)
608/* bits 23-26 TEST */
609/* bits 27-31 reserved */
610
611#define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C))
612#define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20))
613#define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24))
614#define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28))
615
616#define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30))
617#define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34))
618#define RX0FFRC (1<<0)
619#define RX0CLR (1<<1)
620#define RX0STALL (1<<2)
621#define RX0NAK (1<<3)
622#define EP0EN (1<<4)
623#define RX0VOIDINTEN (1<<5)
624#define RX0ERRINTEN (1<<6)
625#define RX0ACKINTEN (1<<7)
626/* bits 8-31 reserved */
627
628#define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38))
629#define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C))
630#define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40))
631#define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44))
632#define TX0CLR (1<<0)
633#define TX0STALL (1<<1)
634#define TX0NAK (1<<2)
635/* bit 3 reserved */
636#define TX0VOIDINTEN (1<<4)
637#define TX0ERRINTEN (1<<5)
638#define TX0ACKINTEN (1<<6)
639/* bits 7-31 reserved */
640
641#define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48))
642#define TX0FULL (1<<0)
643#define TX0URF (1<<1)
644/* bits 2-31 reserved */
645
646#define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C))
647#define TX0DMAINSTA (1<<0)
648/* bits 1-31 reserved */
649
650#define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50))
651#define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54))
652#define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58))
653#define RX1DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x5C))
654#define RX1DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x60))
655#define TX2STAT (*(volatile unsigned long *)(AHB0_UDC + 0x64))
656#define TX2CON (*(volatile unsigned long *)(AHB0_UDC + 0x68))
657#define TX2BUF (*(volatile unsigned long *)(AHB0_UDC + 0x6C))
658#define TX2DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x70))
659#define TX2DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x74))
660#define TX3STAT (*(volatile unsigned long *)(AHB0_UDC + 0x78))
661#define TX3CON (*(volatile unsigned long *)(AHB0_UDC + 0x7C))
662#define TX3BUF (*(volatile unsigned long *)(AHB0_UDC + 0x80))
663#define TX3DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x84))
664#define TX3DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x88))
665#define RX4STAT (*(volatile unsigned long *)(AHB0_UDC + 0x8C))
666#define RX4CON (*(volatile unsigned long *)(AHB0_UDC + 0x90))
667#define RX4DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x94))
668#define RX4DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x98))
669#define TX5STAT (*(volatile unsigned long *)(AHB0_UDC + 0x9C))
670#define TX5CON (*(volatile unsigned long *)(AHB0_UDC + 0xA0))
671#define TX5BUF (*(volatile unsigned long *)(AHB0_UDC + 0xA4))
672#define TX5DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xA8))
673#define TX5DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xAC))
674#define TX6STAT (*(volatile unsigned long *)(AHB0_UDC + 0xB0))
675#define TX6CON (*(volatile unsigned long *)(AHB0_UDC + 0xB4))
676#define TX6BUF (*(volatile unsigned long *)(AHB0_UDC + 0xB8))
677#define TX6DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xBC))
678#define TX6DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xC0))
679#define RX7STAT (*(volatile unsigned long *)(AHB0_UDC + 0xC4))
680#define RX7CON (*(volatile unsigned long *)(AHB0_UDC + 0xC8))
681#define RX7DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0xCC))
682#define RX7DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0xD0))
683#define TX8STAT (*(volatile unsigned long *)(AHB0_UDC + 0xD4))
684#define TX8CON (*(volatile unsigned long *)(AHB0_UDC + 0xD8))
685#define TX8BUF (*(volatile unsigned long *)(AHB0_UDC + 0xDC))
686#define TX8DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xE0))
687#define TX8DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xE4))
688#define TX9STAT (*(volatile unsigned long *)(AHB0_UDC + 0xE8))
689#define TX9CON (*(volatile unsigned long *)(AHB0_UDC + 0xEC))
690#define TX9BUF (*(volatile unsigned long *)(AHB0_UDC + 0xF0))
691#define TX9DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xF4))
692#define TX9DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xF8))
693#define RX10STAT (*(volatile unsigned long *)(AHB0_UDC + 0xFC))
694#define RX10CON (*(volatile unsigned long *)(AHB0_UDC + 0x100))
695#define RX10DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x104))
696#define RX10DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x108))
697#define TX11STAT (*(volatile unsigned long *)(AHB0_UDC + 0x10C))
698#define TX11CON (*(volatile unsigned long *)(AHB0_UDC + 0x110))
699#define TX11BUF (*(volatile unsigned long *)(AHB0_UDC + 0x114))
700#define TX11DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x118))
701#define TX11DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x11C))
702#define TX12STAT (*(volatile unsigned long *)(AHB0_UDC + 0x120))
703#define TX12CON (*(volatile unsigned long *)(AHB0_UDC + 0x124))
704#define TX12BUF (*(volatile unsigned long *)(AHB0_UDC + 0x128))
705#define TX12DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x12C))
706#define TX12DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x130))
707#define RX13STAT (*(volatile unsigned long *)(AHB0_UDC + 0x134))
708#define RX13CON (*(volatile unsigned long *)(AHB0_UDC + 0x138))
709#define RX13DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x13C))
710#define RX13DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x140))
711#define TX14STAT (*(volatile unsigned long *)(AHB0_UDC + 0x144))
712#define TX14CON (*(volatile unsigned long *)(AHB0_UDC + 0x148))
713#define TX14BUF (*(volatile unsigned long *)(AHB0_UDC + 0x14C))
714#define TX14DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x150))
715#define TX14DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x154))
716#define TX15STAT (*(volatile unsigned long *)(AHB0_UDC + 0x158))
717#define TX15CON (*(volatile unsigned long *)(AHB0_UDC + 0x15C))
718#define TX15BUF (*(volatile unsigned long *)(AHB0_UDC + 0x160))
719#define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164))
720#define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168))
721
722/* USB host controller */
723#define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000)
724/* documentation missing */
725
726/* 0x180A8000 - 0x180B0000 reserved */
727
728/* Static/SDRAM memory controller */
729#define AHB0_SDRSTMC (ARM_BUS0_BASE + 0x000B0000)
730#define MCSDR_MODE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x100))
731#define MCSDR_ADDMAP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x104))
732#define MCSDR_ADDCFG (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x108))
733#define MCSDR_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x10C))
734#define MCSDR_T_REF (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x110))
735#define MCSDR_T_RFC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x114))
736#define MCSDR_T_MRD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x118))
737#define MCSDR_T_RP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x120))
738#define MCSDR_T_RCD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x124))
739
740#define MCST0_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x200))
741#define MCST0_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x204))
742#define MCST0_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x208))
743#define MCST0_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x20C))
744#define MCST0_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x210))
745#define MCST0_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x214))
746#define MCST0_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x218))
747#define MCST0_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x21C))
748#define MCST0_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x220))
749
750#define MCST1_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x300))
751#define MCST1_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x304))
752#define MCST1_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x308))
753#define MCST1_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x30C))
754#define MCST1_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x310))
755#define MCST1_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x314))
756#define MCST1_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x318))
757#define MCST1_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x31C))
758#define MCST1_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x320))
759
760/* 0x180B4000 - 0x180C000 reserved */
761
762/* VIP - video input processor */
763#define AHB0_VIP (ARM_BUS0_BASE + 0x000C0000)
764
765/* 0x180C4000 - 0x180E8000 reserved */
766
767/* NAND flash controller */
768#define AHB0_NANDC (ARM_BUS0_BASE + 0x000E8000)
769
770#define FMCTL (*(volatile unsigned long *)(AHB0_NANDC))
771#define FM_RDY (1<<5) /* status of line R/B# */
772#define FM_PROTECT (1<<4) /* WP# line (active low) */
773/* bits 0-3 are chip selects */
774
775#define FMWAIT (*(volatile unsigned long *)(AHB0_NANDC + 0x04))
776#define FLCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x08))
777#define FL_RDY (1<<12)
778#define FL_COR_EN (1<<11)
779#define FL_INT_EN (1<<10)
780#define FL_XFER_EN (1<<9)
781#define FL_INTCLR_EN (1<<8)
782/* bits 3-7 unknown */
783#define FL_START (1<<2)
784#define FL_WR (1<<1)
785#define FL_RST (1<<0)
786
787#define BCHCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x0C))
788/* bit 13 is used but unknown */
789/* bit 12 is used but unknown */
790#define BCH_WR (1<<1)
791#define BCH_RST (1<<0)
792
793#define BCHST (*(volatile unsigned long *)(AHB0_NANDC + 0xD0))
794/* bit 2 ERR ?? */
795/* bit 0 ?? */
796
797#define FLASH_DATA(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x200 + (n<<9)))
798#define FLASH_ADDR(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x204 + (n<<9)))
799#define FLASH_CMD(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x208 + (n<<9)))
800
801#define PAGE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0xA00))
802#define SPARE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0x1200))
803
804#define AHB0_ROM (ARM_BUS0_BASE + 0x000EC000)
805#define AHB0_ES3 (ARM_BUS0_BASE + 0x000F4000)
806#define AHB0_ES4 (ARM_BUS0_BASE + 0x000F8000)
807#define AHB0_ES5 (ARM_BUS0_BASE + 0x000FC000)
808#define AHB0_ES6 (ARM_BUS0_BASE + 0x00100000)
809#define AHB0_EMD_SRAM (ARM_BUS0_BASE + 0x00200000)
810
811/* 0x18204000 - 0x1840000 reserved */
812
813/* 0x18400000 - 0x18484000 reserved*/
814
815#define AHB1_ARBITER 0x18484000
816/* 0x18488000 - 0x186E8000 reserved*/
817
818/* LCD controller */
819#define AHB1_LCDC 0x186E8000
820#define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00))
821/* bits 14-31 reserved */
822#define ALPHA24B (1<<13)
823#define UVBUFEXCH (1<<12)
824#define ALPHA(x) (((x)&0x07)<<9)
825#define Y_MIX (1<<8)
826#define LCDC_MCU (1<<7)
827#define RGB24B (1<<6)
828#define START_EVEN (1<<5)
829#define EVEN_EN (1<<4)
830#define RGB_DUMMY(x) (((x)&0x03)<<2)
831#define LCDC_EN (1<<1)
832#define LCDC_STOP (1<<0)
833#define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04))
834
835#define ALPHA_BASE(x) (((x)&0x3f)<<8)
836#define MCU_CTRL_FIFO_EN (1<<6)
837#define MCU_CTRL_RS_HIGH (1<<5)
838#define MCU_CTRL_BUFF_WRITE (1<<2)
839#define MCU_CTRL_BUFF_START (1<<1)
840#define MCU_CTRL_BYPASS (1<<0)
841
842#define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08))
843#define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C))
844#define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10))
845#define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14))
846#define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x18))
847#define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x1C))
848#define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x20))
849#define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x24))
850#define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28))
851#define LINE_ALPHA_EN (1<<14)
852#define LINE_SCALE_EN (1<<13)
853#define LINE_GBR (1<<12)
854#define LINE_RGB (0<<12)
855#define LINE_YUV_SRC (1<<11)
856#define LINE_RGB_SRC (0<<11)
857/* bits 0-10 Y_BASE */
858
859#define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C))
860#define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30))
861#define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34))
862#define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38))
863#define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C))
864#define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40))
865#define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44))
866#define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48))
867#define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C))
868#define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50))
869#define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54))
870#define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58))
871#define INTR_MASK_LINE (1<<3)
872#define INTR_MASK_EVENLINE (0<<3)
873#define INTR_MASK_BUFF (1<<2)
874#define INTR_MASK_VERT (1<<1)
875#define INTR_MASK_HOR (1<<0)
876
877#define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C))
878#define LCDC_MCU_IDLE (1<<12)
879
880#define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000))
881#define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004))
882
883#define LCD_BUFF (*(volatile unsigned long *)(AHB1_LCDC + 0x2000))
884/* High speed ADC interface */
885#define AHB1_HS_ADC 0x186EC000
886#define HSADC_DATA (*(volatile unsigned long *)(AHB1_HS_ADC + 0x00))
887#define HSADC_CTRL (*(volatile unsigned long *)(AHB1_HS_ADC + 0x04))
888#define HSADC_IER (*(volatile unsigned long *)(AHB1_HS_ADC + 0x08))
889#define HSADC_ISR (*(volatile unsigned long *)(AHB1_HS_ADC + 0x0C))
890
891/* AHB-to-AHB DMA controller */
892#define AHB1_DWDMA 0x186F0000
893#define DWDMA_SAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x00 + 0x58*n))
894#define DWDMA_DAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x08 + 0x58*n))
895#define DWDMA_LLP(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x10 + 0x58*n))
896#define DWDMA_CTL_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x18 + 0x58*n))
897#define CTLL_LLP_SRC_EN (1<<28)
898#define CTLL_LLP_DST_EN (1<<27)
899#define CTLL_SMS_M2 (1<<25)
900#define CTLL_SMS_M1 (0<<25)
901#define CTLL_DMS_M2 (1<<23)
902#define CTLL_DMS_M1 (0<<23)
903#define CTLL_FC_PER2PER (3<<20)
904#define CTLL_FC_PER2MEM (2<<20)
905#define CTLL_FC_MEM2PER (1<<20)
906#define CTLL_FC_MEM2MEM (0<<20)
907/* bit 19 reserved */
908#define CTLL_DST_SCATTER_EN (1<<18)
909#define CTLL_SRC_GATHER_EN (1<<17)
910#define CTLL_SRC_MSIZE_32 (4<<14)
911#define CTLL_SRC_MSIZE_16 (3<<14)
912#define CTLL_SRC_MSIZE_8 (2<<14)
913#define CTLL_SRC_MSIZE_4 (1<<14)
914#define CTLL_SRC_MSIZE_1 (0<<14)
915#define CTLL_DST_MSIZE_32 (4<<11)
916#define CTLL_DST_MSIZE_16 (3<<11)
917#define CTLL_DST_MSIZE_8 (2<<11)
918#define CTLL_DST_MSIZE_4 (1<<11)
919#define CTLL_DST_MSIZE_1 (0<<11)
920#define CTLL_SINC_NO (2<<9)
921#define CTLL_SINC_DEC (1<<9)
922#define CTLL_SINC_INC (0<<9)
923#define CTLL_DINC_NO (2<<7)
924#define CTLL_DINC_DEC (1<<7)
925#define CTLL_DINC_INC (0<<7)
926#define CTLL_SRC_TR_WIDTH_32 (2<<4)
927#define CTLL_SRC_TR_WIDTH_16 (1<<4)
928#define CTLL_SRC_TR_WIDTH_8 (0<<4)
929#define CTLL_DST_TR_WIDTH_32 (2<<1)
930#define CTLL_DST_TR_WIDTH_16 (1<<1)
931#define CTLL_DST_TR_WIDTH_8 (0<<1)
932#define CTLL_INT_EN (1<<0)
933
934#define DWDMA_CTL_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x1C + 0x58*n))
935#define DWDMA_SSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x20 + 0x58*n))
936#define DWDMA_DSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x28 + 0x58*n))
937#define DWDMA_SSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x30 + 0x58*n))
938#define DWDMA_DSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x38 + 0x58*n))
939#define DWDMA_CFG_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x40 + 0x58*n))
940#define CFGL_RELOAD_DST (1<<31)
941#define CFGL_RELOAD_SRC (1<<30)
942#define CFGL_MAX_ABRST(n) ((n)<<20)
943#define CFGL_SRC_HS_POL_LOW (1<<19)
944#define CFGL_DST_HS_POL_LOW (1<<18)
945#define CFGL_LOCK_B (1<<17)
946#define CFGL_LOCK_CH (1<<16)
947#define CFGL_LOCK_B_L(n) (((n)&0x03)<<14)
948#define CFGL_LOCK_CH_L(n) (((n)&0x03)<<12)
949#define CFGL_HS_SEL_SRC (1<<11)
950#define CFGL_HS_SEL_DST (1<<10)
951#define CFGL_FIFO_EMPTY (1<<9)
952#define CFGL_CH_SUSP (1<<8)
953#define CFGL_CH_PRIOR(n) (((n) & 0x03)<<5)
954/* bits 0-4 reserved */
955#define DWDMA_CFG_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x44 + 0x58*n))
956#define CFGH_DST_PER(n) (((n)&0x0F)<<11)
957#define CFGH_SRC_PER(n) (((n)&0x0F)<<7)
958#define CFGH_SRC_UPD_EN (1<<6)
959#define CFGH_DST_UPD_EN (1<<5)
960#define CFGH_PROTCTL(n) (((n)&0x07)<<2)
961#define CFGH_FIFO_MODE (1<<1)
962#define CFGH_FC_MODE (1<<0)
963
964#define DWDMA_SGR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x48 + 0x58*n))
965#define DWDMA_DSR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x50 + 0x58*n))
966
967#define DWDMA_RAW_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C0))
968#define DWDMA_RAW_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C8))
969#define DWDMA_RAW_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D0))
970#define DWDMA_RAW_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D8))
971#define DWDMA_RAW_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E0))
972
973#define DWDMA_STATUS_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E8))
974#define DWDMA_STATUS_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F0))
975#define DWDMA_STATUS_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F8))
976#define DWDMA_STATUS_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x300))
977#define DWDMA_STATUS_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x308))
978
979#define DWDMA_MASK_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x310))
980#define DWDMA_MASK_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x318))
981#define DWDMA_MASK_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x320))
982#define DWDMA_MASK_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x328))
983#define DWDMA_MASK_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x330))
984
985#define DWDMA_CLEAR_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x338))
986#define DWDMA_CLEAR_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x340))
987#define DWDMA_CLEAR_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x348))
988#define DWDMA_CLEAR_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x350))
989#define DWDMA_CLEAR_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x358))
990
991#define DWDMA_STATUS_INT (*(volatile unsigned long *)(AHB1_DWDMA + 0x360))
992
993#define DWDMA_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x368))
994#define DWDMA_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x370))
995#define DWDMA_S_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x378))
996#define DWDMA_S_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x380))
997#define DWDMA_L_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x388))
998#define DWDMA_L_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x390))
999
1000#define DWDMA_DMA_CFG (*(volatile unsigned long *)(AHB1_DWDMA + 0x398))
1001#define GLOB_EN (1<<0)
1002#define DWDMA_DMA_CHEN (*(volatile unsigned long *)(AHB1_DWDMA + 0x3A0))
1003#define DMACHEN_CH0 (0x101<<0)
1004#define DMACHEN_CH1 (0x101<<1)
1005#define DMACHEN_CH2 (0x101<<2)
1006#define DMACHEN_CH3 (0x101<<3)
1007
1008/* ARM7 cache controller */
1009#define ARM_CACHE_CNTRL 0xEFFF0000
1010#define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00))
1011#define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04))
1012#define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08))
1013
1014#define MEMMAPA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x10))
1015#define MEMMAPB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x14))
1016#define MEMMAPC (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x18))
1017#define MEMMAPD (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x1C))
1018#define PFCNTRA_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x20))
1019#define PFCNTRA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x24))
1020#define PFCNTRB_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x28))
1021#define PFCNTRB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x2C))
1022
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-03 11:20:45 +0000