diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-13 06:17:57 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-13 06:17:57 +0000 |
commit | 89fa72f13f8fd841a67f8bd606ccecaa8ed74991 (patch) | |
tree | 1648790b97d577191c343b4da7b459135f95fe71 /firmware/export | |
parent | fdcfc8a77c414b8d009a32e2bd155b967f959e8d (diff) | |
download | rockbox-89fa72f13f8fd841a67f8bd606ccecaa8ed74991.tar.gz rockbox-89fa72f13f8fd841a67f8bd606ccecaa8ed74991.zip |
usb-s3c6400: merge DIEP* and DOEP* in a macro with an extra parameter
minor cosmetics / simplification
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31224 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/usb-s3c6400x.h | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index e8fb4b10a4..c788cd3ed3 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h | |||
@@ -384,10 +384,8 @@ | |||
384 | /** Device IN Token Queue Read Register 4 (RO) */ | 384 | /** Device IN Token Queue Read Register 4 (RO) */ |
385 | #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) | 385 | #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) |
386 | 386 | ||
387 | /* Device Logical IN Endpoint-Specific Registers */ | 387 | /* Device Logical Endpoint-Specific Registers */ |
388 | #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x)))) | 388 | #define DEPCTL(x, out) (*((uint32_t volatile*)(OTGBASE + 0x900 + ((!!out) * 0x200) + 0x20 * (x)))) |
389 | /* Device Logical OUT Endpoint-Specific Registers */ | ||
390 | #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x)))) | ||
391 | /** Maximum Packet Size | 389 | /** Maximum Packet Size |
392 | * IN/OUT EPn | 390 | * IN/OUT EPn |
393 | * IN/OUT EP0 - 2 bits | 391 | * IN/OUT EP0 - 2 bits |
@@ -462,10 +460,8 @@ | |||
462 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ | 460 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ |
463 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ | 461 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ |
464 | 462 | ||
465 | /** Device IN Endpoint (ep) Transfer Size Register */ | 463 | /** Device Endpoint (ep) Transfer Size Register */ |
466 | #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) | 464 | #define DEPTSIZ(x, out) (*((uint32_t volatile*)(OTGBASE + 0x910 + (0x200 * (!!out)) + 0x20 * (x)))) |
467 | /** Device OUT Endpoint (ep) Transfer Size Register */ | ||
468 | #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x)))) | ||
469 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | 465 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ |
470 | #define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */ | 466 | #define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */ |
471 | #define DEPTSIZ_xfersize_bits 0x7ffff | 467 | #define DEPTSIZ_xfersize_bits 0x7ffff |
@@ -483,12 +479,10 @@ | |||
483 | 479 | ||
484 | 480 | ||
485 | /** Device Endpoint (ep) Control Register */ | 481 | /** Device Endpoint (ep) Control Register */ |
486 | #define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) | 482 | #define DEPINT(x,out) (*((uint32_t volatile*)(OTGBASE + 0x908 + (0x200 * (!!out)) + 0x20 * (x)))) |
487 | #define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) | ||
488 | 483 | ||
489 | /** Device Endpoint (ep) DMA Address Register */ | 484 | /** Device Endpoint (ep) DMA Address Register */ |
490 | #define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) | 485 | #define DEPDMA(x,out) (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x)))) |
491 | #define DOEPDMA(x) (*((const void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) | ||
492 | 486 | ||
493 | /* Power and Clock Gating Register */ | 487 | /* Power and Clock Gating Register */ |
494 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) | 488 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) |