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author | Rafaël Carré <rafael.carre@gmail.com> | 2012-01-01 19:21:49 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2012-01-01 19:21:49 +0000 |
commit | 815eba92fdad6a119d9df19d17f4f8db212e54a0 (patch) | |
tree | 9ebdd8827b71a6028ebe259366b11cbd02f10dbc /firmware/export | |
parent | 403decf65d9993e307fd2a900480056ae110c6f0 (diff) | |
download | rockbox-815eba92fdad6a119d9df19d17f4f8db212e54a0.tar.gz rockbox-815eba92fdad6a119d9df19d17f4f8db212e54a0.zip |
GHWCFG* are not as3525v2 specific
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31515 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/as3525v2.h | 39 | ||||
-rw-r--r-- | firmware/export/usb-s3c6400x.h | 37 |
2 files changed, 37 insertions, 39 deletions
diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h index 3778ff7785..4c571f2a22 100644 --- a/firmware/export/as3525v2.h +++ b/firmware/export/as3525v2.h | |||
@@ -45,43 +45,4 @@ | |||
45 | #undef USB_DEVBSS_ATTR | 45 | #undef USB_DEVBSS_ATTR |
46 | #define USB_DEVBSS_ATTR __attribute__((aligned(32))) | 46 | #define USB_DEVBSS_ATTR __attribute__((aligned(32))) |
47 | 47 | ||
48 | #define USBPHY_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset)) | ||
49 | |||
50 | /** User HW Config1 Register */ | ||
51 | #define GHWCFG1 USBPHY_REG(0x044) | ||
52 | #define GHWCFG1_epdir_bitp(ep) (2 * (ep)) | ||
53 | #define GHWCFG1_epdir_bits 0x3 | ||
54 | #define GHWCFG1_EPDIR_BIDIR 0 | ||
55 | #define GHWCFG1_EPDIR_IN 1 | ||
56 | #define GHWCFG1_EPDIR_OUT 2 | ||
57 | |||
58 | /** User HW Config2 Register */ | ||
59 | #define GHWCFG2 USBPHY_REG(0x048) | ||
60 | #define GHWCFG2_arch_bitp 3 /** Architecture */ | ||
61 | #define GHWCFG2_arch_bits 0x3 | ||
62 | #define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ | ||
63 | #define GHWCFG2_hs_phy_type_bits 0x3 | ||
64 | #define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ | ||
65 | #define GHWCFG2_fs_phy_type_bits 0x3 | ||
66 | #define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ | ||
67 | #define GHWCFG2_num_ep_bits 0xf | ||
68 | #define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ | ||
69 | /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ | ||
70 | #define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 | ||
71 | #define GHWCFG2_PHY_TYPE_UTMI 1 | ||
72 | #define GHWCFG2_ARCH_INTERNAL_DMA 2 | ||
73 | |||
74 | /** User HW Config3 Register */ | ||
75 | #define GHWCFG3 USBPHY_REG(0x04C) | ||
76 | #define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ | ||
77 | #define GHWCFG3_dfifo_len_bits 0xffff | ||
78 | |||
79 | /** User HW Config4 Register */ | ||
80 | #define GHWCFG4 USBPHY_REG(0x050) | ||
81 | #define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ | ||
82 | #define GHWCFG4_utmi_phy_data_width_bits 0x3 | ||
83 | #define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ | ||
84 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ | ||
85 | #define GHWCFG4_num_in_ep_bits 0xf | ||
86 | |||
87 | #endif /* __AS3525V2_H__ */ | 48 | #endif /* __AS3525V2_H__ */ |
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index 165ab4e461..55d9b8c93c 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h | |||
@@ -491,4 +491,41 @@ | |||
491 | /* Power and Clock Gating Register */ | 491 | /* Power and Clock Gating Register */ |
492 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) | 492 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) |
493 | 493 | ||
494 | /** User HW Config1 Register */ | ||
495 | #define GHWCFG1 (*((uint32_t volatile*)(OTGBASE + 0x044))) | ||
496 | #define GHWCFG1_epdir_bitp(ep) (2 * (ep)) | ||
497 | #define GHWCFG1_epdir_bits 0x3 | ||
498 | #define GHWCFG1_EPDIR_BIDIR 0 | ||
499 | #define GHWCFG1_EPDIR_IN 1 | ||
500 | #define GHWCFG1_EPDIR_OUT 2 | ||
501 | |||
502 | /** User HW Config2 Register */ | ||
503 | #define GHWCFG2 (*((uint32_t volatile*)(OTGBASE + 0x048))) | ||
504 | #define GHWCFG2_arch_bitp 3 /** Architecture */ | ||
505 | #define GHWCFG2_arch_bits 0x3 | ||
506 | #define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ | ||
507 | #define GHWCFG2_hs_phy_type_bits 0x3 | ||
508 | #define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ | ||
509 | #define GHWCFG2_fs_phy_type_bits 0x3 | ||
510 | #define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ | ||
511 | #define GHWCFG2_num_ep_bits 0xf | ||
512 | #define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ | ||
513 | /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ | ||
514 | #define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 | ||
515 | #define GHWCFG2_PHY_TYPE_UTMI 1 | ||
516 | #define GHWCFG2_ARCH_INTERNAL_DMA 2 | ||
517 | |||
518 | /** User HW Config3 Register */ | ||
519 | #define GHWCFG3 (*((uint32_t volatile*)(OTGBASE + 0x04C))) | ||
520 | #define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ | ||
521 | #define GHWCFG3_dfifo_len_bits 0xffff | ||
522 | |||
523 | /** User HW Config4 Register */ | ||
524 | #define GHWCFG4 (*((uint32_t volatile*)(OTGBASE + 0x050))) | ||
525 | #define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ | ||
526 | #define GHWCFG4_utmi_phy_data_width_bits 0x3 | ||
527 | #define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ | ||
528 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ | ||
529 | #define GHWCFG4_num_in_ep_bits 0xf | ||
530 | |||
494 | #endif /* USB_S3C6400X_H */ | 531 | #endif /* USB_S3C6400X_H */ |