Remove Linux's mmci.h since the license is strict GPLv2

Rewrite a new header distributed under GPLv2 or later, and place it in
export/ in case other targets ship with an ARM PL180 controller

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18959 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 65 insertions, 0 deletions

diff --git a/firmware/export/pl180.h b/firmware/export/pl180.h
new file mode 100644
index 0000000000..98993cc244
--- /dev/null
+++ b/firmware/export/pl180.h
@@ -0,0 +1,65 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright © 2008 Rafaël Carré
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* ARM PrimeCell PL180 SD/MMC controller */
+
+/* MCIStatus bits */
+#define MCI_CMD_CRC_FAIL    (1<<0)
+#define MCI_DATA_CRC_FAIL   (1<<1)
+#define MCI_CMD_TIMEOUT     (1<<2)
+#define MCI_DATA_TIMEOUT    (1<<3)
+#define MCI_TX_UNDERRUN     (1<<4)
+#define MCI_RX_OVERRUN      (1<<5)
+#define MCI_CMD_RESP_END    (1<<6)
+#define MCI_CMD_SENT        (1<<7)
+#define MCI_DATA_END        (1<<8)
+#define MCI_START_BIT_ERR   (1<<9)
+#define MCI_DATA_BLOCK_END  (1<<10)
+#define MCI_CMD_ACTIVE      (1<<11)
+
+
+/* MCIPower bits */
+#define MCI_POWER_OFF           0x0
+/* 0x1 is reserved */
+#define MCI_POWER_UP            0x2
+#define MCI_POWER_ON            0x3
+
+/* bits 5:2 are the voltage */
+
+#define MCI_POWER_OPEN_DRAIN    (1<<6)
+#define MCI_POWER_ROD           (1<<7)
+
+
+/* MCIClock bits */
+/* bits 7:0 are the clock divider */
+#define MCI_CLOCK_ENABLE        (1<<8)
+#define MCI_CLOCK_POWERSAVE     (1<<9)
+#define MCI_CLOCK_BYPASS        (1<<10)
+#define MCI_CLOCK_WIDEBUS       (1<<11)
+
+
+/* MCICommand bits */
+/* bits 5:0 are the command index */
+#define MCI_COMMAND_RESPONSE        (1<<6)
+#define MCI_COMMAND_LONG_RESPONSE   (1<<7)
+#define MCI_COMMAND_INTERRUPT       (1<<8)
+#define MCI_COMMAND_PENDING         (1<<9)
+#define MCI_COMMAND_ENABLE          (1<<10)