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| author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-12-31 18:15:24 +0000 |
|---|---|---|
| committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-12-31 18:15:24 +0000 |
| commit | 5bf0cf59102f6a0fa812d7f60f954b5cc9ab834a (patch) | |
| tree | 410a1436005800874a2ff3939e2671b972901f97 /firmware/export | |
| parent | a2e80d573ca83a66b3aacdf9fe966c9528918c15 (diff) | |
| download | rockbox-5bf0cf59102f6a0fa812d7f60f954b5cc9ab834a.tar.gz rockbox-5bf0cf59102f6a0fa812d7f60f954b5cc9ab834a.zip | |
Ingenic Jz4740:
* Fix compiling
* More USB work
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19628 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/jz4740.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index 4b6008a9ac..409d1d5a6a 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h | |||
| @@ -5102,32 +5102,32 @@ struct Ration2m | |||
| 5102 | #define W_COEF_MSK 0xFF | 5102 | #define W_COEF_MSK 0xFF |
| 5103 | 5103 | ||
| 5104 | // function about REG_CTRL | 5104 | // function about REG_CTRL |
| 5105 | #define stop_ipu(IPU_V_BASE) \ | 5105 | #define IPU_STOP_IPU(IPU_V_BASE) \ |
| 5106 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; | 5106 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; |
| 5107 | 5107 | ||
| 5108 | #define run_ipu(IPU_V_BASE) \ | 5108 | #define IPU_RUN_IPU(IPU_V_BASE) \ |
| 5109 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; | 5109 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; |
| 5110 | 5110 | ||
| 5111 | #define reset_ipu(IPU_V_BASE) \ | 5111 | #define IPU_RESET_IPU(IPU_V_BASE) \ |
| 5112 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; | 5112 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; |
| 5113 | 5113 | ||
| 5114 | #define disable_irq(IPU_V_BASE) \ | 5114 | #define IPU_DISABLE_IRQ(IPU_V_BASE) \ |
| 5115 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; | 5115 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; |
| 5116 | 5116 | ||
| 5117 | #define disable_rsize(IPU_V_BASE) \ | 5117 | #define IPU_DISABLE_RSIZE(IPU_V_BASE) \ |
| 5118 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; | 5118 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; |
| 5119 | 5119 | ||
| 5120 | #define enable_rsize(IPU_V_BASE) \ | 5120 | #define IPU_ENABLE_RSIZE(IPU_V_BASE) \ |
| 5121 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; | 5121 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; |
| 5122 | 5122 | ||
| 5123 | #define ipu_is_enable(IPU_V_BASE) \ | 5123 | #define IPU_IS_ENABLED(IPU_V_BASE) \ |
| 5124 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) | 5124 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) |
| 5125 | 5125 | ||
| 5126 | // function about REG_STATUS | 5126 | // function about REG_STATUS |
| 5127 | #define clear_end_flag(IPU_V_BASE) \ | 5127 | #define IPU_CLEAR_END_FLAG(IPU_V_BASE) \ |
| 5128 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; | 5128 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; |
| 5129 | 5129 | ||
| 5130 | #define polling_end_flag(IPU_V_BASE) \ | 5130 | #define IPU_POLLING_END_FLAG(IPU_V_BASE) \ |
| 5131 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) | 5131 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) |
| 5132 | 5132 | ||
| 5133 | /* parameter | 5133 | /* parameter |