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author | Michael Sevakis <jethead71@rockbox.org> | 2007-07-05 08:21:10 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-07-05 08:21:10 +0000 |
commit | 391e944b8ea930a12f6f1561000a3cc299f4e4d7 (patch) | |
tree | 5c5fa6dddd2db378a03c45c89813949c5cc17b6b /firmware/export | |
parent | 6f36bf448399c5558d49f28cdfbc3ad85f388143 (diff) | |
download | rockbox-391e944b8ea930a12f6f1561000a3cc299f4e4d7.tar.gz rockbox-391e944b8ea930a12f6f1561000a3cc299f4e4d7.zip |
Get rid of yellow plus an optimization I should have seen in the first place.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13794 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/s3c2440.h | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h index 72c33e227c..1eaa77bf80 100644 --- a/firmware/export/s3c2440.h +++ b/firmware/export/s3c2440.h | |||
@@ -78,43 +78,43 @@ | |||
78 | 78 | ||
79 | /* Interrupt indexes - INTOFFSET - IRQ mode only */ | 79 | /* Interrupt indexes - INTOFFSET - IRQ mode only */ |
80 | /* Arbiter 5 => Arbiter 6 Req 5 */ | 80 | /* Arbiter 5 => Arbiter 6 Req 5 */ |
81 | #define ADC_OFFSET 31 /* REQ4 */ | 81 | #define ADC_INTOFFSET 31 /* REQ4 */ |
82 | #define RTC_OFFSET 30 /* REQ3 */ | 82 | #define RTC_INTOFFSET 30 /* REQ3 */ |
83 | #define SPI1_OFFSET 29 /* REQ2 */ | 83 | #define SPI1_INTOFFSET 29 /* REQ2 */ |
84 | #define UART0_OFFSET 28 /* REQ1 */ | 84 | #define UART0_INTOFFSET 28 /* REQ1 */ |
85 | /* Arbiter 4 => Arbiter 6 Req 4 */ | 85 | /* Arbiter 4 => Arbiter 6 Req 4 */ |
86 | #define IIC_OFFSET 27 /* REQ5 */ | 86 | #define IIC_INTOFFSET 27 /* REQ5 */ |
87 | #define USBH_OFFSET 26 /* REQ4 */ | 87 | #define USBH_INTOFFSET 26 /* REQ4 */ |
88 | #define USBD_OFFSET 25 /* REQ3 */ | 88 | #define USBD_INTOFFSET 25 /* REQ3 */ |
89 | #define NFCON_OFFSET 24 /* REQ2 */ | 89 | #define NFCON_INTOFFSET 24 /* REQ2 */ |
90 | #define UART1_OFFSET 23 /* REQ1 */ | 90 | #define UART1_INTOFFSET 23 /* REQ1 */ |
91 | #define SPI0_OFFSET 22 /* REQ0 */ | 91 | #define SPI0_INTOFFSET 22 /* REQ0 */ |
92 | /* Arbiter 3 => Arbiter 6 Req 3 */ | 92 | /* Arbiter 3 => Arbiter 6 Req 3 */ |
93 | #define SDI_OFFSET 21 /* REQ5 */ | 93 | #define SDI_INTOFFSET 21 /* REQ5 */ |
94 | #define DMA3_OFFSET 20 /* REQ4 */ | 94 | #define DMA3_INTOFFSET 20 /* REQ4 */ |
95 | #define DMA2_OFFSET 19 /* REQ3 */ | 95 | #define DMA2_INTOFFSET 19 /* REQ3 */ |
96 | #define DMA1_OFFSET 18 /* REQ2 */ | 96 | #define DMA1_INTOFFSET 18 /* REQ2 */ |
97 | #define DMA0_OFFSET 17 /* REQ1 */ | 97 | #define DMA0_INTOFFSET 17 /* REQ1 */ |
98 | #define LCD_OFFSET 16 /* REQ0 */ | 98 | #define LCD_INTOFFSET 16 /* REQ0 */ |
99 | /* Arbiter 2 => Arbiter 6 Req 2 */ | 99 | /* Arbiter 2 => Arbiter 6 Req 2 */ |
100 | #define UART2_OFFSET 15 /* REQ5 */ | 100 | #define UART2_INTOFFSET 15 /* REQ5 */ |
101 | #define TIMER4_OFFSET 14 /* REQ4 */ | 101 | #define TIMER4_INTOFFSET 14 /* REQ4 */ |
102 | #define TIMER3_OFFSET 13 /* REQ3 */ | 102 | #define TIMER3_INTOFFSET 13 /* REQ3 */ |
103 | #define TIMER2_OFFSET 12 /* REQ2 */ | 103 | #define TIMER2_INTOFFSET 12 /* REQ2 */ |
104 | #define TIMER1_OFFSET 11 /* REQ1 */ | 104 | #define TIMER1_INTOFFSET 11 /* REQ1 */ |
105 | #define TIMER0_OFFSET 10 /* REQ0 */ | 105 | #define TIMER0_INTOFFSET 10 /* REQ0 */ |
106 | /* Arbiter 1 => Arbiter 6 Req 1 */ | 106 | /* Arbiter 1 => Arbiter 6 Req 1 */ |
107 | #define WDT_AC97_OFFSET 9 /* REQ5 */ | 107 | #define WDT_AC97_INTOFFSET 9 /* REQ5 */ |
108 | #define TICK_OFFSET 8 /* REQ4 */ | 108 | #define TICK_INTOFFSET 8 /* REQ4 */ |
109 | #define nBATT_FLT_OFFSET 7 /* REQ3 */ | 109 | #define nBATT_FLT_INTOFFSET 7 /* REQ3 */ |
110 | #define CAM_OFFSET 6 /* REQ2 */ | 110 | #define CAM_INTOFFSET 6 /* REQ2 */ |
111 | #define EINT8_23_OFFSET 5 /* REQ1 */ | 111 | #define EINT8_23_INTOFFSET 5 /* REQ1 */ |
112 | #define EINT4_7_OFFSET 4 /* REQ0 */ | 112 | #define EINT4_7_INTOFFSET 4 /* REQ0 */ |
113 | /* Arbiter 0 => Arbiter 6 Req 0 */ | 113 | /* Arbiter 0 => Arbiter 6 Req 0 */ |
114 | #define EINT3_OFFSET 3 /* REQ4 */ | 114 | #define EINT3_INTOFFSET 3 /* REQ4 */ |
115 | #define EINT2_OFFSET 2 /* REQ3 */ | 115 | #define EINT2_INTOFFSET 2 /* REQ3 */ |
116 | #define EINT1_OFFSET 1 /* REQ2 */ | 116 | #define EINT1_INTOFFSET 1 /* REQ2 */ |
117 | #define EINT0_OFFSET 0 /* REQ1 */ | 117 | #define EINT0_INTOFFSET 0 /* REQ1 */ |
118 | 118 | ||
119 | /* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */ | 119 | /* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */ |
120 | /* Arbiter 5 => Arbiter 6 Req 5 */ | 120 | /* Arbiter 5 => Arbiter 6 Req 5 */ |