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author | Michael Sevakis <jethead71@rockbox.org> | 2017-01-28 14:43:35 -0500 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2017-01-29 19:07:55 -0500 |
commit | 2220a4b695f2f5ac9fe212de4bcfa5365318136f (patch) | |
tree | ef0b31d798b12cbc5cd61e3f020f1856c1759db4 /firmware/export | |
parent | d4303ac900bae6b0fd2320db33bdb4f10861a430 (diff) | |
download | rockbox-2220a4b695f2f5ac9fe212de4bcfa5365318136f.tar.gz rockbox-2220a4b695f2f5ac9fe212de4bcfa5365318136f.zip |
Improve imx31 interrupt code for PMIC and GPIO
Fix stuff that was bugging me about the way I did it at first.
While messing around I found RDS code wasn't masking its GPIO
ISR as it should, which might lead to two different interrupts
messing with the static data.
Change-Id: I54626809ea3039a842af0cc9e3e42853326c4193
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/config/gigabeats.h | 10 | ||||
-rw-r--r-- | firmware/export/mc13783.h | 90 |
2 files changed, 62 insertions, 38 deletions
diff --git a/firmware/export/config/gigabeats.h b/firmware/export/config/gigabeats.h index b20a6934a7..e1bbb18529 100644 --- a/firmware/export/config/gigabeats.h +++ b/firmware/export/config/gigabeats.h | |||
@@ -86,12 +86,6 @@ | |||
86 | 86 | ||
87 | #define AB_REPEAT_ENABLE | 87 | #define AB_REPEAT_ENABLE |
88 | 88 | ||
89 | /* Define this if you have a SI4700 fm radio tuner */ | ||
90 | #define CONFIG_TUNER SI4700 | ||
91 | |||
92 | #define HAVE_RDS_CAP | ||
93 | #define RDS_ISR_PROCESSING | ||
94 | |||
95 | /* Define this if you have the WM8978 audio codec */ | 89 | /* Define this if you have the WM8978 audio codec */ |
96 | #define HAVE_WM8978 | 90 | #define HAVE_WM8978 |
97 | 91 | ||
@@ -124,6 +118,10 @@ | |||
124 | #define HAVE_LCD_ENABLE | 118 | #define HAVE_LCD_ENABLE |
125 | 119 | ||
126 | #ifndef BOOTLOADER | 120 | #ifndef BOOTLOADER |
121 | /* Define this if you have a SI4700 fm radio tuner */ | ||
122 | #define CONFIG_TUNER SI4700 | ||
123 | #define HAVE_RDS_CAP | ||
124 | #define RDS_ISR_PROCESSING | ||
127 | 125 | ||
128 | /* define this if you can flip your LCD */ | 126 | /* define this if you can flip your LCD */ |
129 | #define HAVE_LCD_FLIP | 127 | #define HAVE_LCD_FLIP |
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h index 6ad34346df..d427830786 100644 --- a/firmware/export/mc13783.h +++ b/firmware/export/mc13783.h | |||
@@ -1256,9 +1256,6 @@ enum mc13783_regs_enum | |||
1256 | #define MC13783_TC3PERIOD_POS (21) | 1256 | #define MC13783_TC3PERIOD_POS (21) |
1257 | #define MC13783_TC3TRIODE (0x1 << 23) | 1257 | #define MC13783_TC3TRIODE (0x1 << 23) |
1258 | 1258 | ||
1259 | /* For event enum values which are target-defined */ | ||
1260 | #include "mc13783-target.h" | ||
1261 | |||
1262 | void mc13783_init(void); | 1259 | void mc13783_init(void); |
1263 | void mc13783_close(void); | 1260 | void mc13783_close(void); |
1264 | uint32_t mc13783_set(unsigned address, uint32_t bits); | 1261 | uint32_t mc13783_set(unsigned address, uint32_t bits); |
@@ -1296,7 +1293,7 @@ enum mc13783_int_ids | |||
1296 | MC13783_INT_ID_CHGSHORT = 9, | 1293 | MC13783_INT_ID_CHGSHORT = 9, |
1297 | MC13783_INT_ID_CCCV = 10, | 1294 | MC13783_INT_ID_CCCV = 10, |
1298 | MC13783_INT_ID_CHGCURR = 11, | 1295 | MC13783_INT_ID_CHGCURR = 11, |
1299 | MC13783_INT_ID_BPONI = 12, | 1296 | MC13783_INT_ID_BPON = 12, |
1300 | MC13783_INT_ID_LOBATL = 13, | 1297 | MC13783_INT_ID_LOBATL = 13, |
1301 | MC13783_INT_ID_LOBATH = 14, | 1298 | MC13783_INT_ID_LOBATH = 14, |
1302 | MC13783_INT_ID_UDP = 15, | 1299 | MC13783_INT_ID_UDP = 15, |
@@ -1306,41 +1303,70 @@ enum mc13783_int_ids | |||
1306 | MC13783_INT_ID_CKDET = 22, | 1303 | MC13783_INT_ID_CKDET = 22, |
1307 | MC13783_INT_ID_UDM = 23, | 1304 | MC13783_INT_ID_UDM = 23, |
1308 | /* *STATUS1/MASK1/SENSE1 */ | 1305 | /* *STATUS1/MASK1/SENSE1 */ |
1309 | MC13783_INT_ID_1HZ = 0 + 0x20, | 1306 | MC13783_INT_ID_1HZ = 0 + 32, |
1310 | MC13783_INT_ID_TODA = 1 + 0x20, | 1307 | MC13783_INT_ID_TODA = 1 + 32, |
1311 | MC13783_INT_ID_ONOFD1 = 3 + 0x20, /* ON1B */ | 1308 | MC13783_INT_ID_ONOFD1 = 3 + 32, /* ON1B */ |
1312 | MC13783_INT_ID_ONOFD2 = 4 + 0x20, /* ON2B */ | 1309 | MC13783_INT_ID_ONOFD2 = 4 + 32, /* ON2B */ |
1313 | MC13783_INT_ID_ONOFD3 = 5 + 0x20, /* ON3B */ | 1310 | MC13783_INT_ID_ONOFD3 = 5 + 32, /* ON3B */ |
1314 | MC13783_INT_ID_SYSRST = 6 + 0x20, | 1311 | MC13783_INT_ID_SYSRST = 6 + 32, |
1315 | MC13783_INT_ID_RTCRST = 7 + 0x20, | 1312 | MC13783_INT_ID_RTCRST = 7 + 32, |
1316 | MC13783_INT_ID_PCI = 8 + 0x20, | 1313 | MC13783_INT_ID_PCI = 8 + 32, |
1317 | MC13783_INT_ID_WARM = 9 + 0x20, | 1314 | MC13783_INT_ID_WARM = 9 + 32, |
1318 | MC13783_INT_ID_MEMHLD = 10 + 0x20, | 1315 | MC13783_INT_ID_MEMHLD = 10 + 32, |
1319 | MC13783_INT_ID_PWRRDY = 11 + 0x20, | 1316 | MC13783_INT_ID_PWRRDY = 11 + 32, |
1320 | MC13783_INT_ID_THWARNL = 12 + 0x20, | 1317 | MC13783_INT_ID_THWARNL = 12 + 32, |
1321 | MC13783_INT_ID_THWARNH = 13 + 0x20, | 1318 | MC13783_INT_ID_THWARNH = 13 + 32, |
1322 | MC13783_INT_ID_CLK = 14 + 0x20, | 1319 | MC13783_INT_ID_CLK = 14 + 32, |
1323 | MC13783_INT_ID_SEMAF = 15 + 0x20, | 1320 | MC13783_INT_ID_SEMAF = 15 + 32, |
1324 | MC13783_INT_ID_MC2B = 17 + 0x20, | 1321 | MC13783_INT_ID_MC2B = 17 + 32, |
1325 | MC13783_INT_ID_HSDET = 18 + 0x20, | 1322 | MC13783_INT_ID_HSDET = 18 + 32, |
1326 | MC13783_INT_ID_HSL = 19 + 0x20, | 1323 | MC13783_INT_ID_HSL = 19 + 32, |
1327 | MC13783_INT_ID_ALSPTH = 20 + 0x20, | 1324 | MC13783_INT_ID_ALSPTH = 20 + 32, |
1328 | MC13783_INT_ID_AHSSHORT = 21 + 0x20, | 1325 | MC13783_INT_ID_AHSSHORT = 21 + 32, |
1329 | }; | 1326 | }; |
1330 | 1327 | ||
1331 | #define MC13783_INT_ID_SET_DIV (0x20) | 1328 | #ifdef DEFINE_MC13783_VECTOR_TABLE |
1332 | #define MC13783_INT_ID_NUM_MASK (0x1f) | ||
1333 | 1329 | ||
1334 | struct mc13783_event | 1330 | struct mc13783_event |
1335 | { | 1331 | { |
1336 | enum mc13783_int_ids int_id : 8; | 1332 | uint32_t id : 8; /* MC13783_INT_ID_x */ |
1337 | uint32_t sense : 24; | 1333 | uint32_t sense : 24; /* MC13783_xS */ |
1338 | void (*callback)(void); | 1334 | void (*callback)(void); /* MC13783_EVENT_CB_x */ |
1339 | }; | 1335 | }; |
1340 | 1336 | ||
1341 | void mc13783_enable_event(enum mc13783_event_ids id, bool enable); | 1337 | /* Declares vector table. Order-implied priority */ |
1338 | #define MC13783_EVENT_VECTOR_TBL_START() \ | ||
1339 | static FORCE_INLINE uintptr_t __mc13783_event_vector_tbl(int __what) \ | ||
1340 | { \ | ||
1341 | static const struct mc13783_event __tbl[] = { | ||
1342 | |||
1343 | #define MC13783_EVENT_VECTOR(__name, __sense) \ | ||
1344 | { .id = MC13783_INT_ID_##__name, \ | ||
1345 | .sense = (__sense), \ | ||
1346 | .callback = ({ void MC13783_EVENT_CB_##__name(void); \ | ||
1347 | MC13783_EVENT_CB_##__name; }) }, | ||
1348 | |||
1349 | #define MC13783_EVENT_VECTOR_TBL_END() \ | ||
1350 | }; \ | ||
1351 | switch (__what) \ | ||
1352 | { \ | ||
1353 | default: return (uintptr_t)__tbl; \ | ||
1354 | case 1: return (uintptr_t)ARRAYLEN(__tbl); \ | ||
1355 | } \ | ||
1356 | } | ||
1357 | |||
1358 | #define mc13783_event_vector_tbl \ | ||
1359 | ((const struct mc13783_event *)__mc13783_event_vector_tbl(0)) | ||
1360 | |||
1361 | #define mc13783_event_vector_tbl_len \ | ||
1362 | ((unsigned int)__mc13783_event_vector_tbl(1)) | ||
1363 | |||
1364 | #endif /* DEFINE_MC13783_VECTOR_TABLE */ | ||
1365 | |||
1366 | void mc13783_enable_event(enum mc13783_int_ids id, bool enable); | ||
1342 | 1367 | ||
1343 | /* Read the sense bit if one exists - valid only within event handlers */ | 1368 | /* Read the sense bit(s) if configured - valid only within the respective |
1344 | uint32_t mc13783_event_sense(enum mc13783_event_ids id); | 1369 | event handler */ |
1370 | uint32_t mc13783_event_sense(void); | ||
1345 | 1371 | ||
1346 | #endif /* _MC13783_H_ */ | 1372 | #endif /* _MC13783_H_ */ |