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author | Amaury Pouly <pamaury@rockbox.org> | 2011-07-23 11:45:18 +0000 |
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committer | Amaury Pouly <pamaury@rockbox.org> | 2011-07-23 11:45:18 +0000 |
commit | 06c94740e510d0ce04e069f34631a0539e9e6742 (patch) | |
tree | 64035ab2001e3820ab0dd61e328d5fa16140f4c0 /firmware/export | |
parent | 3f8bf5e041fe052c859f283c9309118f3e791440 (diff) | |
download | rockbox-06c94740e510d0ce04e069f34631a0539e9e6742.tar.gz rockbox-06c94740e510d0ce04e069f34631a0539e9e6742.zip |
imx233/fuze+: prepare target to enable MMU
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30199 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
-rw-r--r-- | firmware/export/imx233.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/firmware/export/imx233.h b/firmware/export/imx233.h index 182442c2ab..682240ac40 100644 --- a/firmware/export/imx233.h +++ b/firmware/export/imx233.h | |||
@@ -24,12 +24,14 @@ | |||
24 | #define IRAM_ORIG 0 | 24 | #define IRAM_ORIG 0 |
25 | #define IRAM_SIZE 0x8000 | 25 | #define IRAM_SIZE 0x8000 |
26 | #define DRAM_ORIG 0x40000000 | 26 | #define DRAM_ORIG 0x40000000 |
27 | #define DRAM_SIZE 0x20000000 | 27 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) |
28 | 28 | ||
29 | #define TTB_BASE_ADDR (DRAM_ORIG + (MEMORYSIZE*0x100000) - TTB_SIZE) | 29 | #define TTB_BASE_ADDR (IRAM_ORIG + IRAM_SIZE - TTB_SIZE) |
30 | #define TTB_SIZE (0x4000) | 30 | #define TTB_SIZE 0x4000 |
31 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) | 31 | #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) |
32 | #define FRAME_SIZE (240*320*2) | 32 | #define FRAME_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8) |
33 | #define LCD_FRAME_ADDR (DRAM_ORIG + DRAM_SIZE - FRAME_SIZE) | ||
34 | #define FRAME ((unsigned short *)LCD_FRAME_ADDR) | ||
33 | 35 | ||
34 | /* USBOTG */ | 36 | /* USBOTG */ |
35 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) | 37 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) |
@@ -48,5 +50,7 @@ | |||
48 | #define __BLOCK_SFTRST (1 << 31) | 50 | #define __BLOCK_SFTRST (1 << 31) |
49 | #define __BLOCK_CLKGATE (1 << 30) | 51 | #define __BLOCK_CLKGATE (1 << 30) |
50 | 52 | ||
53 | #define CACHEALIGN_BITS 4 | ||
54 | |||
51 | 55 | ||
52 | #endif /* __IMX233_H__ */ | 56 | #endif /* __IMX233_H__ */ |