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author | Frank Gevaerts <frank@gevaerts.be> | 2008-11-30 15:43:15 +0000 |
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committer | Frank Gevaerts <frank@gevaerts.be> | 2008-11-30 15:43:15 +0000 |
commit | caaf3c0b97b59117cacd221ed4557b2fd351b5b3 (patch) | |
tree | 476ae3869a0d20821b2cf3afd1e5ab737299878a /firmware/export/usb-tcc.h | |
parent | 5f7db212d591213ae98d7b051b828bc65b792f2a (diff) | |
download | rockbox-caaf3c0b97b59117cacd221ed4557b2fd351b5b3.tar.gz rockbox-caaf3c0b97b59117cacd221ed4557b2fd351b5b3.zip |
Move tcc77x/usb-tcc77x.c to usb-tcc.c as it is more general than just tcc77x (even usb-tcc is too specific, but I don't know anything better)
Add #if0ed USB defines to config-cowond2.h, so experimenting with USB is easy
Add dummy set_serial_descriptor() implementation to usb_core.c. This one doesn't generate a unique serial, so it must never be used for non-testing purposes. When usaed, a compiler warning will be generated
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19273 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/usb-tcc.h')
-rw-r--r-- | firmware/export/usb-tcc.h | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/firmware/export/usb-tcc.h b/firmware/export/usb-tcc.h new file mode 100644 index 0000000000..787977312f --- /dev/null +++ b/firmware/export/usb-tcc.h | |||
@@ -0,0 +1,116 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 Vitja Makarov | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef USB_TCC7XX_H | ||
22 | #define USB_TCC7XX_H | ||
23 | |||
24 | #define MMR_REG16(base, x) (*(volatile unsigned short *) ((base) + (x))) | ||
25 | |||
26 | /* USB PHY registers */ | ||
27 | #define TCC7xx_USB_PHY_CFG MMR_REG16(USB_BASE, 0xc4) | ||
28 | #define TCC7xx_USB_PHY_CFG_XSEL (1<<13) /* FS/HS Transceiver enable */ | ||
29 | #define TCC7xx_USB_PHY_CFG_DWS (1<<6) /* Host mode */ | ||
30 | #define TCC7xx_USB_PHY_XO (1<<5) /* Enable XO_OUT */ | ||
31 | #define TCC7xx_USB_PHY_CKSEL_12 0 | ||
32 | #define TCC7xx_USB_PHY_CKSEL_24 1 | ||
33 | #define TCC7xx_USB_PHY_CKSEL_48 2 | ||
34 | |||
35 | /* USB 2.0 device registers */ | ||
36 | #define TCC7xx_USB_INDEX MMR_REG16(USB_BASE, 0x00) /* Endpoint Index register */ | ||
37 | #define TCC7xx_USB_EPIF MMR_REG16(USB_BASE, 0x04) /* Endpoint interrupt flag register */ | ||
38 | #define TCC7xx_USB_EPIE MMR_REG16(USB_BASE, 0x08) /* Endpoint interrupt enable register */ | ||
39 | #define TCC7xx_USB_FUNC MMR_REG16(USB_BASE, 0x0c) /* Function address register */ | ||
40 | #define TCC7xx_USB_EP_DIR MMR_REG16(USB_BASE, 0x14) /* Endpoint direction register */ | ||
41 | #define TCC7xx_USB_TST MMR_REG16(USB_BASE, 0x14) /* Test registerregister */ | ||
42 | #define TCC7xx_USB_SYS_STAT MMR_REG16(USB_BASE, 0x1c) /* System status register */ | ||
43 | #define TCC7xx_USB_SYS_STAT_RESET (1<<0) /* Host forced reced */ | ||
44 | #define TCC7xx_USB_SYS_STAT_SUSPEND (1<<1) /* Host forced suspend */ | ||
45 | #define TCC7xx_USB_SYS_STAT_RESUME (1<<2) /* Host forced resume */ | ||
46 | #define TCC7xx_USB_SYS_STAT_HIGH (1<<4) /* High speed */ | ||
47 | #define TCC7xx_USB_SYS_STAT_SPD_END (1<<6) /* Speed detection end */ | ||
48 | #define TCC7xx_USB_SYS_STAT_VBON (1<<8) | ||
49 | #define TCC7xx_USB_SYS_STAT_VBOF (1<<9) | ||
50 | #define TCC7xx_USB_SYS_STAT_EOERR (1<<10) /* overrun error */ | ||
51 | #define TCC7xx_USB_SYS_STAT_DCERR (1<<11) /* Data CRC error */ | ||
52 | #define TCC7xx_USB_SYS_STAT_TCERR (1<<12) /* Token CRC error */ | ||
53 | #define TCC7xx_USB_SYS_STAT_BSERR (1<<13) /* Bit-stuff error */ | ||
54 | #define TCC7xx_USB_SYS_STAT_TMERR (1<<14) /* Timeout error */ | ||
55 | #define TCC7xx_USB_SYS_STAT_BAERR (1<<15) /* Byte align error */ | ||
56 | |||
57 | #define TCC7xx_USB_SYS_STAT_ERRORS (TCC7xx_USB_SYS_STAT_EOERR | \ | ||
58 | TCC7xx_USB_SYS_STAT_DCERR | \ | ||
59 | TCC7xx_USB_SYS_STAT_TCERR | \ | ||
60 | TCC7xx_USB_SYS_STAT_BSERR | \ | ||
61 | TCC7xx_USB_SYS_STAT_TMERR | \ | ||
62 | TCC7xx_USB_SYS_STAT_BAERR) | ||
63 | |||
64 | #define TCC7xx_USB_SYS_CTRL MMR_REG16(USB_BASE, 0x20) /* System control register */ | ||
65 | #define TCC7xx_USB_SYS_CTRL_RESET (1<<0) /* Reset enable */ | ||
66 | #define TCC7xx_USB_SYS_CTRL_SUSPEND (1<<1) /* Suspend enable */ | ||
67 | #define TCC7xx_USB_SYS_CTRL_RESUME (1<<2) /* Resume enable */ | ||
68 | #define TCC7xx_USB_SYS_CTRL_IPS (1<<4) /* Interrupt polarity */ | ||
69 | #define TCC7xx_USB_SYS_CTRL_RFRE (1<<5) /* Reverse read data enable */ | ||
70 | #define TCC7xx_USB_SYS_CTRL_SPDEN (1<<6) /* Speed detection interrupt enable */ | ||
71 | #define TCC7xx_USB_SYS_CTRL_BUS16 (1<<7) /* Select bus width 8/16 */ | ||
72 | #define TCC7xx_USB_SYS_CTRL_EIEN (1<<8) /* Error interrupt enable */ | ||
73 | #define TCC7xx_USB_SYS_CTRL_RWDE (1<<9) /* Reverse write data enable */ | ||
74 | #define TCC7xx_USB_SYS_CTRL_VBONE (1<<10) /* VBus On enable */ | ||
75 | #define TCC7xx_USB_SYS_CTRL_VBOFE (1<<11) /* VBus Off enable */ | ||
76 | #define TCC7xx_USB_SYS_CTRL_DUAL (1<<12) /* Dual interrupt enable*/ | ||
77 | #define TCC7xx_USB_SYS_CTRL_DMAZ (1<<14) /* DMA total count zero int */ | ||
78 | |||
79 | #define TCC7xx_USB_EP0_STAT MMR_REG16(USB_BASE, 0x24) /* EP0 status register */ | ||
80 | #define TCC7xx_USB_EP0_CTRL MMR_REG16(USB_BASE, 0x28) /* EP0 control register */ | ||
81 | |||
82 | #define TCC7xx_USB_EP0_BUF MMR_REG16(USB_BASE, 0x60) /* EP0 buffer register */ | ||
83 | #define TCC7xx_USB_EP1_BUF MMR_REG16(USB_BASE, 0x64) /* EP1 buffer register */ | ||
84 | #define TCC7xx_USB_EP2_BUF MMR_REG16(USB_BASE, 0x68) /* EP2 buffer register */ | ||
85 | #define TCC7xx_USB_EP3_BUF MMR_REG16(USB_BASE, 0x6c) /* EP3 buffer register */ | ||
86 | |||
87 | /* Indexed registers, write endpoint number to TCC7xx_USB_INDEX */ | ||
88 | #define TCC7xx_USB_EP_STAT MMR_REG16(USB_BASE, 0x2c) /* EP status register */ | ||
89 | #define TCC7xx_USP_EP_STAT_RPS (1 << 0) /* Packet received */ | ||
90 | #define TCC7xx_USP_EP_STAT_TPS (1 << 1) /* Packet transmited */ | ||
91 | #define TCC7xx_USP_EP_STAT_LWO (1 << 4) /* Last word odd */ | ||
92 | #define TCC7xx_USB_EP_CTRL MMR_REG16(USB_BASE, 0x30) /* EP control register */ | ||
93 | #define TCC7xx_USB_EP_CTRL_TZLS (1 << 0) /* TX Zero Length Set */ | ||
94 | #define TCC7xx_USB_EP_CTRL_ESS (1 << 1) /* Endpoint Stall Set */ | ||
95 | #define TCC7xx_USB_EP_CTRL_CDP (1 << 2) /* Clear Data PID */ | ||
96 | #define TCC7xx_USB_EP_CTRL_TTE (1 << 5) /* TX Toggle Enable */ | ||
97 | #define TCC7xx_USB_EP_CTRL_FLUSH (1 << 6) /* Flush FIFO */ | ||
98 | #define TCC7xx_USB_EP_CTRL_DUEN (1 << 7) /* Dual FIFO Mode */ | ||
99 | #define TCC7xx_USB_EP_CTRL_IME (1 << 8) /* ISO Mode */ | ||
100 | #define TCC7xx_USB_EP_CTRL_OUTHD (1 << 11) /* OUT Packet Hold */ | ||
101 | #define TCC7xx_USB_EP_CTRL_INHLD (1 << 12) /* IN Packet Hold */ | ||
102 | |||
103 | #define TCC7xx_USB_EP_BRCR MMR_REG16(USB_BASE, 0x34) /* EP byte read count register */ | ||
104 | #define TCC7xx_USB_EP_BWCR MMR_REG16(USB_BASE, 0x38) /* EP byte write count register */ | ||
105 | #define TCC7xx_USB_EP_MAXP MMR_REG16(USB_BASE, 0x3c) /* EP max packet register */ | ||
106 | |||
107 | #define TCC7xx_USB_EP_DMA_CTRL MMR_REG16(USB_BASE, 0x40) /* EP DMA control register */ | ||
108 | #define TCC7xx_USB_EP_DMA_TCNTR MMR_REG16(USB_BASE, 0x44) /* EP DMA transfer counter register */ | ||
109 | #define TCC7xx_USB_EP_DMA_FCNTR MMR_REG16(USB_BASE, 0x48) /* EP DMA fifo counter register */ | ||
110 | #define TCC7xx_USB_EP_DMA_TTCNTR1 MMR_REG16(USB_BASE, 0x4c) /* EP DMA total trasfer counter1 register */ | ||
111 | #define TCC7xx_USB_EP_DMA_TTCNTR2 MMR_REG16(USB_BASE, 0x50) /* EP DMA total trasfer counter2 register */ | ||
112 | #define TCC7xx_USB_EP_DMA_ADDR1 MMR_REG16(USB_BASE, 0xa0) /* EP DMA MCU addr1 register */ | ||
113 | #define TCC7xx_USB_EP_DMA_ADDR2 MMR_REG16(USB_BASE, 0xa4) /* EP DMA MCU addr2 register */ | ||
114 | #define TCC7xx_USB_EP_DMA_STAT MMR_REG16(USB_BASE, 0xc0) /* EP DMA Transfer Status register */ | ||
115 | #define TCC7xx_USB_DELAY_CTRL MMR_REG16(USB_BASE, 0x80) /* Delay control register */ | ||
116 | #endif /* USB_TCC7XX_H */ | ||