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authorRob Purchase <shotofadds@rockbox.org>2009-03-30 21:15:15 +0000
committerRob Purchase <shotofadds@rockbox.org>2009-03-30 21:15:15 +0000
commit75b37696fba2e0c5c1e9f28449fda7d6c7f9a9ac (patch)
tree30d308bcc748733e5eefd7684aafa2d7e62c67a1 /firmware/export/tcc780x.h
parent8739af490e03e243848720c5987f566a56479136 (diff)
downloadrockbox-75b37696fba2e0c5c1e9f28449fda7d6c7f9a9ac.tar.gz
rockbox-75b37696fba2e0c5c1e9f28449fda7d6c7f9a9ac.zip
TCC78x: Implement the user timer, rework some of the timer register #defines, and use udelay() instead of the hacky sleep_ms() in the D2 LCD driver. Doom works now.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20585 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/tcc780x.h')
-rw-r--r--firmware/export/tcc780x.h41
1 files changed, 29 insertions, 12 deletions
diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h
index b10b311fed..3ff910fce7 100644
--- a/firmware/export/tcc780x.h
+++ b/firmware/export/tcc780x.h
@@ -132,20 +132,37 @@
132 132
133/* Timer / Counters */ 133/* Timer / Counters */
134 134
135#define TCFG0 (*(volatile unsigned long *)0xF3003000) 135/* Note: Timers 0-3 have a 16 bit counter, 4-5 have 20 bits */
136#define TCNT0 (*(volatile unsigned long *)0xF3003004) 136#define TCFG(_x_) (*(volatile unsigned int *)(0xF3003000+0x10*(_x_)))
137#define TREF0 (*(volatile unsigned long *)0xF3003008) 137#define TCNT(_x_) (*(volatile unsigned int *)(0xF3003004+0x10*(_x_)))
138#define TCFG1 (*(volatile unsigned long *)0xF3003010) 138#define TREF(_x_) (*(volatile unsigned int *)(0xF3003008+0x10*(_x_)))
139#define TCNT1 (*(volatile unsigned long *)0xF3003014) 139
140#define TREF1 (*(volatile unsigned long *)0xF3003018) 140#define TIREQ (*(volatile unsigned long *)0xF3003060)
141 141
142#define TIREQ (*(volatile unsigned long *)0xF3003060) 142/* TCFG flags */
143#define TCFG_EN (1<<0) /* enable timer */
144#define TCFG_CONT (1<<1) /* continue from zero once TREF is reached */
145#define TCFG_PWM (1<<2) /* PWM mode */
146#define TCFG_IEN (1<<3) /* IRQ enable */
147#define TCFG_SEL (1<<4) /* clock source & divider */
148#define TCFG_POL (1<<7) /* polarity */
149#define TCFG_CLEAR (1<<8) /* reset TCNT to zero */
150#define TCFG_STOP (1<<9) /* stop counting once TREF reached */
143 151
144/* TIREQ flags */ 152/* TIREQ flags */
145#define TF0 (1<<8) /* Timer 0 reference value reached */ 153#define TIREQ_TI0 (1<<0) /* Timer N IRQ flag */
146#define TF1 (1<<9) /* Timer 1 reference value reached */ 154#define TIREQ_TI1 (1<<1)
147#define TI0 (1<<0) /* Timer 0 IRQ flag */ 155#define TIREQ_TI2 (1<<2)
148#define TI1 (1<<1) /* Timer 1 IRQ flag */ 156#define TIREQ_TI3 (1<<3)
157#define TIREQ_TI4 (1<<4)
158#define TIREQ_TI5 (1<<5)
159
160#define TIREQ_TF0 (1<<8) /* Timer N reference value reached */
161#define TIREQ_TF1 (1<<9)
162#define TIREQ_TF2 (1<<10)
163#define TIREQ_TF3 (1<<11)
164#define TIREQ_TF4 (1<<12)
165#define TIREQ_TF5 (1<<13)
149 166
150#define TC32EN (*(volatile unsigned long *)0xF3003080) 167#define TC32EN (*(volatile unsigned long *)0xF3003080)
151#define TC32LDV (*(volatile unsigned long *)0xF3003084) 168#define TC32LDV (*(volatile unsigned long *)0xF3003084)