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author | Jens Arnold <amiconn@rockbox.org> | 2007-04-11 23:51:00 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2007-04-11 23:51:00 +0000 |
commit | 8636e6949e802556da1588b814e454155358df90 (patch) | |
tree | fb668ba4b210d21185ee6f46a8e80e61171af8bf /firmware/export/system.h | |
parent | b16137e10b0b309ccd9bf81fb2d70f24b090aa7d (diff) | |
download | rockbox-8636e6949e802556da1588b814e454155358df90.tar.gz rockbox-8636e6949e802556da1588b814e454155358df90.zip |
Moved SH1 system code to target tree. * First shot at hwcompat cleanup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13114 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/system.h')
-rw-r--r-- | firmware/export/system.h | 100 |
1 files changed, 2 insertions, 98 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index ea3092537c..b32d1d3a21 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -196,110 +196,14 @@ enum { | |||
196 | }; | 196 | }; |
197 | 197 | ||
198 | #ifndef SIMULATOR | 198 | #ifndef SIMULATOR |
199 | #ifdef CPU_COLDFIRE | 199 | #if defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440) || (CONFIG_CPU == SH7034) |
200 | #include "system-target.h" | 200 | #include "system-target.h" |
201 | #endif | 201 | #endif |
202 | #endif | 202 | #endif |
203 | #ifndef SIMULATOR | ||
204 | #if CONFIG_CPU == S3C2440 | ||
205 | #include "system-target.h" | ||
206 | #endif | ||
207 | #endif | ||
208 | |||
209 | #if CONFIG_CPU == SH7034 | ||
210 | #define or_b(mask, address) \ | ||
211 | asm \ | ||
212 | ("or.b %0,@(r0,gbr)" \ | ||
213 | : \ | ||
214 | : /* %0 */ I_CONSTRAINT((char)(mask)), \ | ||
215 | /* %1 */ "z"(address-GBR)) | ||
216 | |||
217 | #define and_b(mask, address) \ | ||
218 | asm \ | ||
219 | ("and.b %0,@(r0,gbr)" \ | ||
220 | : \ | ||
221 | : /* %0 */ I_CONSTRAINT((char)(mask)), \ | ||
222 | /* %1 */ "z"(address-GBR)) | ||
223 | |||
224 | #define xor_b(mask, address) \ | ||
225 | asm \ | ||
226 | ("xor.b %0,@(r0,gbr)" \ | ||
227 | : \ | ||
228 | : /* %0 */ I_CONSTRAINT((char)(mask)), \ | ||
229 | /* %1 */ "z"(address-GBR)) | ||
230 | |||
231 | |||
232 | #endif /* CONFIG_CPU == SH7034 */ | ||
233 | 203 | ||
234 | #ifndef SIMULATOR | 204 | #ifndef SIMULATOR |
235 | 205 | ||
236 | /**************************************************************************** | 206 | #if defined(CPU_ARM) |
237 | * Interrupt level setting | ||
238 | * The level is left shifted 4 bits | ||
239 | ****************************************************************************/ | ||
240 | #if CONFIG_CPU == SH7034 | ||
241 | #define HIGHEST_IRQ_LEVEL (15<<4) | ||
242 | static inline int set_irq_level(int level) | ||
243 | { | ||
244 | int i; | ||
245 | /* Read the old level and set the new one */ | ||
246 | asm volatile ("stc sr, %0" : "=r" (i)); | ||
247 | asm volatile ("ldc %0, sr" : : "r" (level)); | ||
248 | return i; | ||
249 | } | ||
250 | |||
251 | static inline uint16_t swap16(uint16_t value) | ||
252 | /* | ||
253 | result[15..8] = value[ 7..0]; | ||
254 | result[ 7..0] = value[15..8]; | ||
255 | */ | ||
256 | { | ||
257 | uint16_t result; | ||
258 | asm volatile ("swap.b\t%1,%0" : "=r"(result) : "r"(value)); | ||
259 | return result; | ||
260 | } | ||
261 | |||
262 | static inline uint32_t SWAW32(uint32_t value) | ||
263 | /* | ||
264 | result[31..16] = value[15.. 0]; | ||
265 | result[15.. 0] = value[31..16]; | ||
266 | */ | ||
267 | { | ||
268 | uint32_t result; | ||
269 | asm volatile ("swap.w\t%1,%0" : "=r"(result) : "r"(value)); | ||
270 | return result; | ||
271 | } | ||
272 | |||
273 | static inline uint32_t swap32(uint32_t value) | ||
274 | /* | ||
275 | result[31..24] = value[ 7.. 0]; | ||
276 | result[23..16] = value[15.. 8]; | ||
277 | result[15.. 8] = value[23..16]; | ||
278 | result[ 7.. 0] = value[31..24]; | ||
279 | */ | ||
280 | { | ||
281 | asm volatile ("swap.b\t%0,%0\n" | ||
282 | "swap.w\t%0,%0\n" | ||
283 | "swap.b\t%0,%0\n" : "+r"(value)); | ||
284 | return value; | ||
285 | } | ||
286 | |||
287 | static inline uint32_t swap_odd_even32(uint32_t value) | ||
288 | { | ||
289 | /* | ||
290 | result[31..24],[15.. 8] = value[23..16],[ 7.. 0] | ||
291 | result[23..16],[ 7.. 0] = value[31..24],[15.. 8] | ||
292 | */ | ||
293 | asm volatile ("swap.b\t%0,%0\n" | ||
294 | "swap.w\t%0,%0\n" | ||
295 | "swap.b\t%0,%0\n" | ||
296 | "swap.w\t%0,%0\n" : "+r"(value)); | ||
297 | return value; | ||
298 | } | ||
299 | |||
300 | #define invalidate_icache() | ||
301 | |||
302 | #elif defined(CPU_ARM) | ||
303 | 207 | ||
304 | /* TODO: Implement set_irq_level and check CPU frequencies */ | 208 | /* TODO: Implement set_irq_level and check CPU frequencies */ |
305 | 209 | ||