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authorCástor Muñoz <cmvidal@gmail.com>2014-11-10 01:50:19 +0100
committerMarcin Bukat <marcin.bukat@gmail.com>2014-11-13 23:00:33 +0100
commitedb0c6c92f40db70be778bf9162ff116f5f01e31 (patch)
tree3bd981c07eb9f6c549fe4319f0f31a424b8741e4 /firmware/export/s5l8702.h
parentbcca1114383c2147e60e73825ec68403c90bea40 (diff)
downloadrockbox-edb0c6c92f40db70be778bf9162ff116f5f01e31.tar.gz
rockbox-edb0c6c92f40db70be778bf9162ff116f5f01e31.zip
iPod Classic: fix s5l8702 cache line length.
Use 32 bytes for cache line length (arm926ej-s), this prevents misalignments of ATA storage buffer which in some builds could cause weird faults. Change-Id: I88dc595d251315620ec49b0251ddc039ff47181e Reviewed-on: http://gerrit.rockbox.org/1031 Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Diffstat (limited to 'firmware/export/s5l8702.h')
-rw-r--r--firmware/export/s5l8702.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h
index b7da971b49..8e1d827f54 100644
--- a/firmware/export/s5l8702.h
+++ b/firmware/export/s5l8702.h
@@ -30,7 +30,7 @@
30 30
31#define TIMER_FREQ 54000000 31#define TIMER_FREQ 54000000
32 32
33#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 33#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
34 34
35#define DRAM_ORIG 0x08000000 35#define DRAM_ORIG 0x08000000
36#define IRAM_ORIG 0 36#define IRAM_ORIG 0