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authorDave Chapman <dave@dchapman.com>2009-07-16 18:03:09 +0000
committerDave Chapman <dave@dchapman.com>2009-07-16 18:03:09 +0000
commit715d8c63d9a051b2ab7ab6ac27639d090a1823f1 (patch)
tree4ea5cfb387d17dc0745b7fca413ca027e1db07e1 /firmware/export/s5l8700.h
parentf8ec7e4ad457a7a3a428f18eaf35f50a28d752b4 (diff)
downloadrockbox-715d8c63d9a051b2ab7ab6ac27639d090a1823f1.tar.gz
rockbox-715d8c63d9a051b2ab7ab6ac27639d090a1823f1.zip
Add auto-detection of Nano 2G LCD type, and an initial attempt at lcd_update() for the second lcd type. This lcd_update works, but not reliably.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21905 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/s5l8700.h')
-rw-r--r--firmware/export/s5l8700.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index 940f47f7f2..353690398a 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -459,6 +459,10 @@
459#define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 7 */ 459#define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 7 */
460#define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 10 */ 460#define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 10 */
461#define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 10 */ 461#define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 10 */
462#define PCON13 (*(REG32_PTR_T)(0x3CF000D0)) /* Configures the pins of port 13 */
463#define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */
464#define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */
465#define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */
462#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ 466#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */
463#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ 467#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
464#define PCON11 (*(REG32_PTR_T)(0x3CF000F8)) /* Configures the pins of port 11 */ 468#define PCON11 (*(REG32_PTR_T)(0x3CF000F8)) /* Configures the pins of port 11 */