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| author | Dave Chapman <dave@dchapman.com> | 2009-09-17 07:36:09 +0000 |
|---|---|---|
| committer | Dave Chapman <dave@dchapman.com> | 2009-09-17 07:36:09 +0000 |
| commit | d67c4d2f6ba5bde26ca6e121064d4da116e868c5 (patch) | |
| tree | 2769b9fff7e8e555e19d8ace569e77b4177fae77 /firmware/export/s5l8700.h | |
| parent | 8dae933293223e28648ec72ac818ab2a98ee2482 (diff) | |
| download | rockbox-d67c4d2f6ba5bde26ca6e121064d4da116e868c5.tar.gz rockbox-d67c4d2f6ba5bde26ca6e121064d4da116e868c5.zip | |
Add PLL2 definitions for the S5L8701, plus some config file tweaks for the Nano2G
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22715 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/s5l8700.h')
| -rw-r--r-- | firmware/export/s5l8700.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 4360f14a2d..cfd8e59ad6 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
| @@ -108,8 +108,10 @@ | |||
| 108 | #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ | 108 | #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ |
| 109 | #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ | 109 | #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ |
| 110 | #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ | 110 | #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ |
| 111 | #define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value Register - S5L8701 only? */ | ||
| 111 | #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ | 112 | #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ |
| 112 | #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ | 113 | #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ |
| 114 | #define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ | ||
| 113 | #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ | 115 | #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ |
| 114 | #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ | 116 | #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ |
| 115 | #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ | 117 | #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ |