From d67c4d2f6ba5bde26ca6e121064d4da116e868c5 Mon Sep 17 00:00:00 2001 From: Dave Chapman Date: Thu, 17 Sep 2009 07:36:09 +0000 Subject: Add PLL2 definitions for the S5L8701, plus some config file tweaks for the Nano2G git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22715 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/s5l8700.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'firmware/export/s5l8700.h') diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 4360f14a2d..cfd8e59ad6 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h @@ -108,8 +108,10 @@ #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ +#define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value Register - S5L8701 only? */ #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ +#define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ -- cgit v1.2.3