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author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-04 09:15:50 +0100 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-04 09:18:12 +0100 |
commit | e1ea08417bca57c607df6686472fa0a86f38b6d1 (patch) | |
tree | a30a9676c4262ecd83aa3fe28f9159852184c6da /firmware/export/rk27xx.h | |
parent | f551d14bdd1f6160b06e739334b5e0150e645f10 (diff) | |
download | rockbox-e1ea08417bca57c607df6686472fa0a86f38b6d1.tar.gz rockbox-e1ea08417bca57c607df6686472fa0a86f38b6d1.zip |
rk27xx: introduce meaningfull constants in usb driver
Based on pamaury's work. No (un)functional change yet.
Change-Id: I7fe76c1da20d87d6c92eb3792e3d352877d423d7
Diffstat (limited to 'firmware/export/rk27xx.h')
-rw-r--r-- | firmware/export/rk27xx.h | 100 |
1 files changed, 72 insertions, 28 deletions
diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h index c75004c5f7..3ca2bc089d 100644 --- a/firmware/export/rk27xx.h +++ b/firmware/export/rk27xx.h | |||
@@ -555,8 +555,19 @@ | |||
555 | #define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00)) | 555 | #define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00)) |
556 | #define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04)) | 556 | #define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04)) |
557 | #define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08)) | 557 | #define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08)) |
558 | #define DEV_RMTWKP (1<<2) | ||
559 | #define DEV_SELF_PWR (1<<3) | ||
560 | #define DEV_SOFT_CN (1<<4) | ||
561 | #define DEV_RESUME (1<<5) | ||
562 | #define DEV_PHY16BIT (1<<6) | ||
563 | #define SOFT_POR (1<<7) | ||
564 | #define CSR_DONE (1<<8) | ||
558 | 565 | ||
559 | #define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10)) | 566 | #define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10)) |
567 | #define DEV_EN (1<<7) | ||
568 | #define VBUS_STS (1<<20) | ||
569 | #define DEV_SPEED (3<<21) | ||
570 | |||
560 | #define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14)) | 571 | #define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14)) |
561 | #define EN_SOF_INTR (1<<0) | 572 | #define EN_SOF_INTR (1<<0) |
562 | #define EN_SETUP_INTR (1<<1) | 573 | #define EN_SETUP_INTR (1<<1) |
@@ -592,7 +603,7 @@ | |||
592 | #define USBRST_INTR (1<<4) | 603 | #define USBRST_INTR (1<<4) |
593 | #define RESUME_INTR (1<<5) | 604 | #define RESUME_INTR (1<<5) |
594 | #define SUSP_INTR (1<<6) | 605 | #define SUSP_INTR (1<<6) |
595 | /* bit 7 reserved */ | 606 | #define CONN_INTR (1<<7) /* marked as reserved in DS */ |
596 | #define BOUT1_INTR (1<<8) | 607 | #define BOUT1_INTR (1<<8) |
597 | #define BIN2_INTR (1<<9) | 608 | #define BIN2_INTR (1<<9) |
598 | #define IIN3_INTR (1<<10) | 609 | #define IIN3_INTR (1<<10) |
@@ -612,44 +623,21 @@ | |||
612 | /* bits 27-31 reserved */ | 623 | /* bits 27-31 reserved */ |
613 | 624 | ||
614 | #define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C)) | 625 | #define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C)) |
626 | #define UDC_INTEN (1<<0) | ||
627 | #define UDC_INTEDGE_TRIG (1<<1) | ||
628 | #define UDC_INTHIGH_ACT (1<<2) | ||
629 | |||
615 | #define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20)) | 630 | #define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20)) |
616 | #define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24)) | 631 | #define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24)) |
617 | #define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28)) | 632 | #define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28)) |
618 | |||
619 | #define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30)) | 633 | #define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30)) |
620 | #define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34)) | 634 | #define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34)) |
621 | #define RX0FFRC (1<<0) | ||
622 | #define RX0CLR (1<<1) | ||
623 | #define RX0STALL (1<<2) | ||
624 | #define RX0NAK (1<<3) | ||
625 | #define EP0EN (1<<4) | ||
626 | #define RX0VOIDINTEN (1<<5) | ||
627 | #define RX0ERRINTEN (1<<6) | ||
628 | #define RX0ACKINTEN (1<<7) | ||
629 | /* bits 8-31 reserved */ | ||
630 | |||
631 | #define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38)) | 635 | #define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38)) |
632 | #define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C)) | 636 | #define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C)) |
633 | #define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40)) | 637 | #define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40)) |
634 | #define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44)) | 638 | #define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44)) |
635 | #define TX0CLR (1<<0) | ||
636 | #define TX0STALL (1<<1) | ||
637 | #define TX0NAK (1<<2) | ||
638 | /* bit 3 reserved */ | ||
639 | #define TX0VOIDINTEN (1<<4) | ||
640 | #define TX0ERRINTEN (1<<5) | ||
641 | #define TX0ACKINTEN (1<<6) | ||
642 | /* bits 7-31 reserved */ | ||
643 | |||
644 | #define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48)) | 639 | #define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48)) |
645 | #define TX0FULL (1<<0) | ||
646 | #define TX0URF (1<<1) | ||
647 | /* bits 2-31 reserved */ | ||
648 | |||
649 | #define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C)) | 640 | #define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C)) |
650 | #define TX0DMAINSTA (1<<0) | ||
651 | /* bits 1-31 reserved */ | ||
652 | |||
653 | #define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50)) | 641 | #define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50)) |
654 | #define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54)) | 642 | #define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54)) |
655 | #define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58)) | 643 | #define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58)) |
@@ -722,6 +710,62 @@ | |||
722 | #define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164)) | 710 | #define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164)) |
723 | #define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168)) | 711 | #define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168)) |
724 | 712 | ||
713 | /* RXnSTAT bits */ | ||
714 | /* bits 10:0 RXLEN */ | ||
715 | /* bits 15:11 reserved */ | ||
716 | #define RXVOID (1<<16) | ||
717 | #define RXERR (1<<17) | ||
718 | #define RXACK (1<<18) | ||
719 | #define RXCFINT (1<<19) /* reserved for EP0 */ | ||
720 | /* bits 23:20 reserved */ | ||
721 | #define RXFULL (1<<24) | ||
722 | #define RXOVF (1<<25) | ||
723 | /* bits 31:26 reserved */ | ||
724 | |||
725 | /* RXnCON bits */ | ||
726 | #define RXFFRC (1<<0) | ||
727 | #define RXCLR (1<<1) | ||
728 | #define RXSTALL (1<<2) | ||
729 | #define RXNAK (1<<3) | ||
730 | #define RXEPEN (1<<4) | ||
731 | #define RXVOIDINTEN (1<<5) | ||
732 | #define RXERRINTEN (1<<6) | ||
733 | #define RXACKINTEN (1<<7) | ||
734 | /* bits 31:8 reserved for EP0 */ | ||
735 | /* bits 31:14 reserved for others */ | ||
736 | |||
737 | /* TxnSTAT */ | ||
738 | /* bits 10:0 TXLEN */ | ||
739 | /* bits 15:11 reserved */ | ||
740 | #define TXVOID (1<<16) | ||
741 | #define TXERR (1<<17) | ||
742 | #define TXACK (1<<18) | ||
743 | #define TXDMADN (1<<19) /* reserved for EP0 */ | ||
744 | #define TXCFINT (1<<20) /* reserved for EP0 */ | ||
745 | /* bits 31:21 reserved */ | ||
746 | |||
747 | /* TXnCON bits */ | ||
748 | #define TXCLR (1<<0) | ||
749 | #define TXSTALL (1<<1) | ||
750 | #define TXNAK (1<<2) | ||
751 | #define TXEPEN (1<<3) /* reserved for EP0 */ | ||
752 | #define TXVOIDINTEN (1<<4) | ||
753 | #define TXERRINTEN (1<<5) | ||
754 | #define TXACKINTEN (1<<6) | ||
755 | #define TXDMADNEN (1<<7) /* reserved for EP0 */ | ||
756 | /* bits 31:8 reserved */ | ||
757 | |||
758 | /* TXnBUF bits */ | ||
759 | #define TXFULL (1<<0) | ||
760 | #define TXURF (1<<1) | ||
761 | #define TXDS0 (1<<2) /* reserved for EP0 */ | ||
762 | #define TXDS1 (1<<3) /* reserved for EP0 */ | ||
763 | /* bits 31:4 reserved */ | ||
764 | |||
765 | /* DMA bits */ | ||
766 | #define DMA_START (1<<0) | ||
767 | /* bits 31:1 reserved */ | ||
768 | |||
725 | /* USB host controller */ | 769 | /* USB host controller */ |
726 | #define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000) | 770 | #define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000) |
727 | /* documentation missing */ | 771 | /* documentation missing */ |