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author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-17 08:44:09 +0100 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2013-01-10 20:23:41 +0100 |
commit | 2b6dfdb34e8e750528b91276c504f1664dfdef4c (patch) | |
tree | 17dd8a0b5cbdc18600e59c16a076f2580948d88c /firmware/export/rk27xx.h | |
parent | 1fa406dc216cbbabd9f17df6312abf205976276f (diff) | |
download | rockbox-2b6dfdb34e8e750528b91276c504f1664dfdef4c.tar.gz rockbox-2b6dfdb34e8e750528b91276c504f1664dfdef4c.zip |
rk27xx: substitute magic constants with meaningful names for clock gating
Change-Id: I6c66c7496db3db78e5c959414464826134dbe200
Diffstat (limited to 'firmware/export/rk27xx.h')
-rw-r--r-- | firmware/export/rk27xx.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h index 3ca2bc089d..6fb69d46c1 100644 --- a/firmware/export/rk27xx.h +++ b/firmware/export/rk27xx.h | |||
@@ -124,6 +124,38 @@ | |||
124 | #define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10)) | 124 | #define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10)) |
125 | #define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14)) | 125 | #define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14)) |
126 | #define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18)) | 126 | #define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18)) |
127 | #define CLKCFG_OTP (1<<0) | ||
128 | #define CLKCFG_DSP (1<<1) | ||
129 | #define CLKCFG_SDRAM (1<<2) | ||
130 | #define CLKCFG_HDMA (1<<3) | ||
131 | #define CLKCFG_DWDMA (1<<4) | ||
132 | #define CLKCFG_UHC (1<<5) | ||
133 | #define CLKCFG_UDC (1<<6) | ||
134 | /* 7 - 8 reserved */ | ||
135 | #define CLKCFG_NAND (1<<9) | ||
136 | #define CLKCFG_A2A (1<<10) | ||
137 | #define CLKCFG_SRAM (1<<11) | ||
138 | #define CLKCFG_HCLK_LCDC (1<<12) | ||
139 | #define CLKCFG_LCDC (1<<13) | ||
140 | #define CLKCFG_HCLK_VIP (1<<14) | ||
141 | #define CLKCFG_VIP (1<<15) | ||
142 | #define CLKCFG_I2S (1<<16) | ||
143 | #define CLKCFG_PCLK_I2S (1<<17) | ||
144 | #define CLKCFG_UART0 (1<<18) | ||
145 | #define CLKCFG_UART1 (1<<19) | ||
146 | #define CLKCFG_I2C (1<<20) | ||
147 | #define CLKCFG_SPI (1<<21) | ||
148 | #define CLKCFG_SD (1<<22) | ||
149 | #define CLKCFG_PCLK_LSADC (1<<23) | ||
150 | #define CLKCFG_LSADC (1<<24) | ||
151 | #define CLKCFG_HCLK_HSADC (1<<25) | ||
152 | #define CLKCFG_HSADC (1<<26) | ||
153 | #define CLKCFG_GPIO (1<<27) | ||
154 | #define CLKCFG_TIMER (1<<28) | ||
155 | #define CLKCFG_PWM (1<<29) | ||
156 | #define CLKCFG_RTC (1<<30) | ||
157 | #define CLKCFG_WDT (1<<31) | ||
158 | |||
127 | #define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C)) | 159 | #define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C)) |
128 | #define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20)) | 160 | #define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20)) |
129 | #define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24)) | 161 | #define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24)) |