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author | Michael Sevakis <jethead71@rockbox.org> | 2007-10-16 01:25:17 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-10-16 01:25:17 +0000 |
commit | a9b2fb5ee3114fe835f6515b6aeae7454f66d821 (patch) | |
tree | fc4e96d0c1f215565918406c8827b16b806c1345 /firmware/export/pp5020.h | |
parent | a3fbbc9fa7e12fd3fce122bbd235dc362050e024 (diff) | |
download | rockbox-a9b2fb5ee3114fe835f6515b6aeae7454f66d821.tar.gz rockbox-a9b2fb5ee3114fe835f6515b6aeae7454f66d821.zip |
Finally full multicore support for PortalPlayer 502x targets with an eye towards the possibility of other types. All SVN targets the low-lag code to speed up blocking operations. Most files are modified here simple due to a name change to actually support a real event object and a param change to create_thread. Add some use of new features but just sit on things for a bit and leave full integration for later. Work will continue on to address size on sensitive targets and simplify things if possible. Any PP target having problems with SWP can easily be changed to sw corelocks with one #define change in config.h though only PP5020 has shown an issue and seems to work without any difficulties.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15134 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/pp5020.h')
-rw-r--r-- | firmware/export/pp5020.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 5654a7de63..b591bce695 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
@@ -34,11 +34,15 @@ | |||
34 | /* Each processor has two mailboxes it can write to and two which | 34 | /* Each processor has two mailboxes it can write to and two which |
35 | it can read from. We define the first to be for sending messages | 35 | it can read from. We define the first to be for sending messages |
36 | and the second for replying to messages */ | 36 | and the second for replying to messages */ |
37 | #define CPU_MESSAGE (*(volatile unsigned long *)(0x60001000)) | 37 | #define CPU_MESSAGE (*(volatile unsigned long *)(0x60001000)) |
38 | #define COP_MESSAGE (*(volatile unsigned long *)(0x60001004)) | 38 | #define COP_MESSAGE (*(volatile unsigned long *)(0x60001004)) |
39 | #define CPU_REPLY (*(volatile unsigned long *)(0x60001008)) | 39 | #define CPU_REPLY (*(volatile unsigned long *)(0x60001008)) |
40 | #define COP_REPLY (*(volatile unsigned long *)(0x6000100c)) | 40 | #define COP_REPLY (*(volatile unsigned long *)(0x6000100c)) |
41 | #define MBOX_CONTROL (*(volatile unsigned long *)(0x60001010)) | 41 | #define MBOX_CONTROL (*(volatile unsigned long *)(0x60001010)) |
42 | |||
43 | /* Simple convenient array-like access */ | ||
44 | #define PROC_MESSAGE(core) ((&CPU_MESSAGE)[core]) | ||
45 | #define PROC_REPLY(core) ((&CPU_REPLY)[core]) | ||
42 | 46 | ||
43 | /* Interrupts */ | 47 | /* Interrupts */ |
44 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000)) | 48 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000)) |
@@ -142,6 +146,7 @@ | |||
142 | /* Processors Control */ | 146 | /* Processors Control */ |
143 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) | 147 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) |
144 | #define COP_CTL (*(volatile unsigned long *)(0x60007004)) | 148 | #define COP_CTL (*(volatile unsigned long *)(0x60007004)) |
149 | #define PROC_CTL(core) ((&CPU_CTL)[core]) | ||
145 | 150 | ||
146 | #define PROC_SLEEP 0x80000000 | 151 | #define PROC_SLEEP 0x80000000 |
147 | #define PROC_WAIT 0x40000000 | 152 | #define PROC_WAIT 0x40000000 |