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| author | William Wilgus <wilgus.william@gmail.com> | 2021-03-29 10:04:04 -0400 |
|---|---|---|
| committer | William Wilgus <wilgus.william@gmail.com> | 2021-04-01 00:52:57 -0400 |
| commit | 89acde6af2c9d8ff4a647e7abd737b18333cad80 (patch) | |
| tree | 92c9ec13b6292c1cbc2abf6b0692fff49e95cd02 /firmware/export/pp5020.h | |
| parent | 058a9ec9453fed05872d10c72913bbc7034d32d8 (diff) | |
| download | rockbox-89acde6af2c9d8ff4a647e7abd737b18333cad80.tar.gz rockbox-89acde6af2c9d8ff4a647e7abd737b18333cad80.zip | |
H10 PP Crash -- Fixed
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Diffstat (limited to 'firmware/export/pp5020.h')
| -rw-r--r-- | firmware/export/pp5020.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 073d33e494..0d2ffc4d94 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
| @@ -584,8 +584,10 @@ | |||
| 584 | #define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000)) | 584 | #define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000)) |
| 585 | /* 0xf0002000-0xf0003fff */ | 585 | /* 0xf0002000-0xf0003fff */ |
| 586 | #define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000)) | 586 | #define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000)) |
| 587 | /* 0xf0004000-0xf0007fff */ | 587 | /* 0xf0004000-0xf0005fff */ |
| 588 | #define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000)) | 588 | #define CACHE_STATUS_BASE_CPU (*(volatile unsigned long*)(0xf0004000)) |
| 589 | /* 0xf0006000-0xf0007fff */ | ||
| 590 | #define CACHE_STATUS_BASE_COP (*(volatile unsigned long*)(0xf0006000)) | ||
| 589 | #define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000)) | 591 | #define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000)) |
| 590 | #define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000)) | 592 | #define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000)) |
| 591 | #define MMAP_PHYS_READ_MASK 0x0100 | 593 | #define MMAP_PHYS_READ_MASK 0x0100 |