diff options
author | Barry Wardell <rockbox@barrywardell.net> | 2007-03-03 23:37:17 +0000 |
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committer | Barry Wardell <rockbox@barrywardell.net> | 2007-03-03 23:37:17 +0000 |
commit | 169ebdbda7d805e83de06cd013759e6281d5db34 (patch) | |
tree | cbc23eea79cceb9611ee825ce3070d12d4b80db8 /firmware/export/pp5020.h | |
parent | 8b061252c4359aa960ae31c0a4b2ba92f6771017 (diff) | |
download | rockbox-169ebdbda7d805e83de06cd013759e6281d5db34.tar.gz rockbox-169ebdbda7d805e83de06cd013759e6281d5db34.zip |
Some more replacing of inl/outl with register #define's (doesn't change end-result binary). Add lots more #define's based on the ipodlinux wiki and some extrapolation.
Also add PortalPlayer SoC version to the HW info debug screen.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12575 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/pp5020.h')
-rw-r--r-- | firmware/export/pp5020.h | 128 |
1 files changed, 104 insertions, 24 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index ade1f138a0..3d205a0ea1 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h | |||
@@ -31,30 +31,71 @@ | |||
31 | #define PROC_ID_COP 0xaa | 31 | #define PROC_ID_COP 0xaa |
32 | 32 | ||
33 | /* Interrupts */ | 33 | /* Interrupts */ |
34 | #define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) | 34 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) |
35 | #define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) | 35 | #define COP_INT_STAT (*(volatile unsigned long*)(0x60004004)) |
36 | #define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) | 36 | #define CPU_FIQ_STAT (*(volatile unsigned long*)(0x60004008)) |
37 | #define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) | 37 | #define COP_FIQ_STAT (*(volatile unsigned long*)(0x6000400c)) |
38 | #define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000)) | 38 | |
39 | #define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) | 39 | #define INT_STAT (*(volatile unsigned long*)(0x60004010)) |
40 | 40 | #define INT_FORCED_STAT (*(volatile unsigned long*)(0x60004014)) | |
41 | #define INT_FORCED_SET (*(volatile unsigned long*)(0x60004018)) | ||
42 | #define INT_FORCED_CLR (*(volatile unsigned long*)(0x6000401c)) | ||
43 | |||
44 | #define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020)) | ||
45 | #define CPU_INT_EN (*(volatile unsigned long*)(0x60004024)) | ||
46 | #define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028)) | ||
47 | #define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c)) | ||
48 | |||
49 | #define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030)) | ||
50 | #define COP_INT_EN (*(volatile unsigned long*)(0x60004034)) | ||
51 | #define COP_INT_CLR (*(volatile unsigned long*)(0x60004038)) | ||
52 | #define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c)) | ||
53 | |||
54 | #define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100)) | ||
55 | #define COP_HI_INT_STAT (*(volatile unsigned long*)(0x60004104)) | ||
56 | #define CPU_HI_FIQ_STAT (*(volatile unsigned long*)(0x60004108)) | ||
57 | #define COP_HI_FIQ_STAT (*(volatile unsigned long*)(0x6000410c)) | ||
58 | |||
59 | #define HI_INT_STAT (*(volatile unsigned long*)(0x60004110)) | ||
60 | #define HI_INT_FORCED_STAT (*(volatile unsigned long*)(0x60004114)) | ||
61 | #define HI_INT_FORCED_SET (*(volatile unsigned long*)(0x60004118)) | ||
62 | #define HI_INT_FORCED_CLR (*(volatile unsigned long*)(0x6000411c)) | ||
63 | |||
64 | #define CPU_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004120)) | ||
65 | #define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124)) | ||
66 | #define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128)) | ||
67 | #define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c)) | ||
68 | |||
69 | #define COP_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004130)) | ||
70 | #define COP_HI_INT_EN (*(volatile unsigned long*)(0x60004134)) | ||
71 | #define COP_HI_INT_CLR (*(volatile unsigned long*)(0x60004138)) | ||
72 | #define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c)) | ||
73 | |||
41 | #define TIMER1_IRQ 0 | 74 | #define TIMER1_IRQ 0 |
42 | #define TIMER2_IRQ 1 | 75 | #define TIMER2_IRQ 1 |
76 | #define MAILBOX_IRQ 4 | ||
43 | #define I2S_IRQ 10 | 77 | #define I2S_IRQ 10 |
44 | #define IDE_IRQ 23 | 78 | #define IDE_IRQ 23 |
79 | #define USB_IRQ 24 | ||
80 | #define FIREWIRE_IRQ 25 | ||
81 | #define HI_IRQ 30 | ||
45 | #define GPIO_IRQ (32+0) | 82 | #define GPIO_IRQ (32+0) |
46 | #define SER0_IRQ (32+4) | 83 | #define SER0_IRQ (32+4) |
47 | #define SER1_IRQ (32+5) | 84 | #define SER1_IRQ (32+5) |
48 | #define I2C_IRQ (32+8) | 85 | #define I2C_IRQ (32+8) |
49 | 86 | ||
50 | #define TIMER1_MASK (1 << TIMER1_IRQ) | 87 | #define TIMER1_MASK (1 << TIMER1_IRQ) |
51 | #define TIMER2_MASK (1 << TIMER2_IRQ) | 88 | #define TIMER2_MASK (1 << TIMER2_IRQ) |
52 | #define I2S_MASK (1 << I2S_IRQ) | 89 | #define MAILBOX_MASK (1 << MAILBOX_IRQ) |
53 | #define IDE_MASK (1 << IDE_IRQ) | 90 | #define I2S_MASK (1 << I2S_IRQ) |
54 | #define GPIO_MASK (1 << (GPIO_IRQ-32)) | 91 | #define IDE_MASK (1 << IDE_IRQ) |
55 | #define SER0_MASK (1 << (SER0_IRQ-32)) | 92 | #define USB_MASK (1 << USB_IRQ) |
56 | #define SER1_MASK (1 << (SER1_IRQ-32)) | 93 | #define FIREWIRE_MASK (1 << FIREWIRE_IRQ) |
57 | #define I2C_MASK (1 << (I2C_IRQ-32)) | 94 | #define HI_MASK (1 << HI_IRQ) |
95 | #define GPIO_MASK (1 << (GPIO_IRQ-32)) | ||
96 | #define SER0_MASK (1 << (SER0_IRQ-32)) | ||
97 | #define SER1_MASK (1 << (SER1_IRQ-32)) | ||
98 | #define I2C_MASK (1 << (I2C_IRQ-32)) | ||
58 | 99 | ||
59 | /* Timers */ | 100 | /* Timers */ |
60 | #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) | 101 | #define TIMER1_CFG (*(volatile unsigned long *)(0x60005000)) |
@@ -62,14 +103,22 @@ | |||
62 | #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) | 103 | #define TIMER2_CFG (*(volatile unsigned long *)(0x60005008)) |
63 | #define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) | 104 | #define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c)) |
64 | #define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) | 105 | #define USEC_TIMER (*(volatile unsigned long *)(0x60005010)) |
106 | #define RTC (*(volatile unsigned long *)(0x60005014)) | ||
65 | 107 | ||
66 | /* Device Controller */ | 108 | /* Device Controller */ |
67 | #define DEV_RS (*(volatile unsigned long *)(0x60006004)) | 109 | #define DEV_RS (*(volatile unsigned long *)(0x60006004)) |
68 | #define DEV_EN (*(volatile unsigned long *)(0x6000600c)) | 110 | #define DEV_EN (*(volatile unsigned long *)(0x6000600c)) |
69 | 111 | ||
70 | #define DEV_SYSTEM 0x4 | 112 | #define DEV_SYSTEM 0x4 |
71 | #define DEV_I2C 0x1000 | 113 | #define DEV_SER0 0x40 |
72 | #define DEV_USB 0x400000 | 114 | #define DEV_SER1 0x80 |
115 | #define DEV_I2S 0x800 | ||
116 | #define DEV_I2C 0x1000 | ||
117 | #define DEV_OPTO 0x10000 | ||
118 | #define DEV_PIEZO 0x10000 | ||
119 | #define DEV_USB 0x400000 | ||
120 | #define DEV_FIREWIRE 0x800000 | ||
121 | #define DEV_IDE0 0x2000000 | ||
73 | 122 | ||
74 | /* Processors Control */ | 123 | /* Processors Control */ |
75 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) | 124 | #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) |
@@ -186,12 +235,11 @@ | |||
186 | #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) | 235 | #define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c)) |
187 | 236 | ||
188 | /* Device initialization */ | 237 | /* Device initialization */ |
189 | #define DEV_INIT (*(volatile unsigned long *)(0x70000020)) | 238 | #define PP_VER1 (*(volatile unsigned long *)(0x70000000)) |
239 | #define PP_VER2 (*(volatile unsigned long *)(0x70000004)) | ||
240 | #define DEV_INIT (*(volatile unsigned long *)(0x70000020)) | ||
190 | 241 | ||
191 | #define INIT_USB 0x80000000 | 242 | #define INIT_USB 0x80000000 |
192 | |||
193 | /* I2C */ | ||
194 | #define I2C_BASE 0x7000c000 | ||
195 | 243 | ||
196 | /* I2S */ | 244 | /* I2S */ |
197 | #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) | 245 | #define IISCONFIG (*(volatile unsigned long*)(0x70002800)) |
@@ -199,10 +247,40 @@ | |||
199 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) | 247 | #define IISFIFO_WR (*(volatile unsigned long*)(0x70002840)) |
200 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) | 248 | #define IISFIFO_RD (*(volatile unsigned long*)(0x70002880)) |
201 | 249 | ||
250 | /* Serial Controller */ | ||
251 | #define SERIAL0 (*(volatile unsigned long*)(0x70006000)) | ||
252 | #define SERIAL1 (*(volatile unsigned long*)(0x70006040)) | ||
253 | |||
254 | /* I2C */ | ||
255 | #define I2C_BASE 0x7000c000 | ||
256 | |||
257 | /* EIDE Controller */ | ||
258 | #define IDE0_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000000)) | ||
259 | #define IDE0_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000004)) | ||
260 | #define IDE0_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000008)) | ||
261 | #define IDE0_SEC_TIMING1 (*(volatile unsigned long*)(0xc300000c)) | ||
262 | |||
263 | #define IDE1_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000010)) | ||
264 | #define IDE1_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000014)) | ||
265 | #define IDE1_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000018)) | ||
266 | #define IDE1_SEC_TIMING1 (*(volatile unsigned long*)(0xc300001c)) | ||
267 | |||
268 | #define IDE0_CFG (*(volatile unsigned long*)(0xc3000028)) | ||
269 | #define IDE1_CFG (*(volatile unsigned long*)(0xc300002c)) | ||
270 | |||
271 | #define IDE0_CNTRLR_STAT (*(volatile unsigned long*)(0xc30001e0)) | ||
272 | |||
202 | /* USB controller */ | 273 | /* USB controller */ |
203 | #define USB_BASE 0xc5000000 | 274 | #define USB_BASE 0xc5000000 |
275 | |||
276 | /* Firewire Controller */ | ||
277 | #define FIREWIRE_BASE 0xc6000000 | ||
204 | 278 | ||
205 | /* Memory controller */ | 279 | /* Memory controller */ |
280 | #define CACHE_BASE (*(volatile unsigned long*)(0xf0000000)) | ||
281 | #define CACHE_INIT_BASE (*(volatile unsigned long*)(0xf0004000)) | ||
282 | #define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000)) | ||
283 | #define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000)) | ||
206 | #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) | 284 | #define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000)) |
207 | #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) | 285 | #define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004)) |
208 | #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) | 286 | #define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008)) |
@@ -211,5 +289,7 @@ | |||
211 | #define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014)) | 289 | #define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014)) |
212 | #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) | 290 | #define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018)) |
213 | #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) | 291 | #define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c)) |
292 | #define CACHE_CTRL1 (*(volatile unsigned long*)(0xf000f020)) | ||
293 | #define CACHE_CTRL2 (*(volatile unsigned long*)(0xf000f024)) | ||
214 | 294 | ||
215 | #endif | 295 | #endif |