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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-07-14 15:03:10 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-07-14 15:03:10 +0000 |
commit | 0709f0a5c60b5525ff98708887f5f1e5b0b570c2 (patch) | |
tree | 849fd125aa7b217228d584212d2930d8259ff5d8 /firmware/export/mips.h | |
parent | 4f199817488708ba60724accb6ce76886f855af8 (diff) | |
download | rockbox-0709f0a5c60b5525ff98708887f5f1e5b0b570c2.tar.gz rockbox-0709f0a5c60b5525ff98708887f5f1e5b0b570c2.zip |
Add preliminary support for the Onda VX747 (MIPS target)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18032 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/mips.h')
-rwxr-xr-x | firmware/export/mips.h | 820 |
1 files changed, 820 insertions, 0 deletions
diff --git a/firmware/export/mips.h b/firmware/export/mips.h new file mode 100755 index 0000000000..6f73d150b2 --- /dev/null +++ b/firmware/export/mips.h | |||
@@ -0,0 +1,820 @@ | |||
1 | /************************************************************************** | ||
2 | * * | ||
3 | * PROJECT : MIPS port for uC/OS-II * | ||
4 | * * | ||
5 | * MODULE : MIPS.h * | ||
6 | * * | ||
7 | * AUTHOR : Michael Anburaj * | ||
8 | * URL : http://geocities.com/michaelanburaj/ * | ||
9 | * EMAIL: michaelanburaj@hotmail.com * | ||
10 | * * | ||
11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * | ||
12 | * * | ||
13 | * TOOL-CHAIN : SDE & Cygnus * | ||
14 | * * | ||
15 | * DESCRIPTION : * | ||
16 | * MIPS processor definitions. * | ||
17 | * The basic CPU definitions are found in the file archdefs.h, which * | ||
18 | * is included by mips.h. * | ||
19 | * * | ||
20 | * mips.h implements aliases for some of the definitions in archdefs.h * | ||
21 | * and adds various definitions. * | ||
22 | * * | ||
23 | **************************************************************************/ | ||
24 | |||
25 | |||
26 | #ifndef __MIPS_H__ | ||
27 | #define __MIPS_H__ | ||
28 | |||
29 | #include "mips-archdefs.h" | ||
30 | |||
31 | |||
32 | /* ********************************************************************* */ | ||
33 | /* Module configuration */ | ||
34 | |||
35 | |||
36 | /* ********************************************************************* */ | ||
37 | /* Interface macro & data definition */ | ||
38 | |||
39 | #ifndef MSK | ||
40 | #define MSK(n) ((1 << (n)) - 1) | ||
41 | #endif | ||
42 | |||
43 | /* CPU registers */ | ||
44 | #define SYS_CPUREG_ZERO 0 | ||
45 | #define SYS_CPUREG_AT 1 | ||
46 | #define SYS_CPUREG_V0 2 | ||
47 | #define SYS_CPUREG_V1 3 | ||
48 | #define SYS_CPUREG_A0 4 | ||
49 | #define SYS_CPUREG_A1 5 | ||
50 | #define SYS_CPUREG_A2 6 | ||
51 | #define SYS_CPUREG_A3 7 | ||
52 | #define SYS_CPUREG_T0 8 | ||
53 | #define SYS_CPUREG_T1 9 | ||
54 | #define SYS_CPUREG_T2 10 | ||
55 | #define SYS_CPUREG_T3 11 | ||
56 | #define SYS_CPUREG_T4 12 | ||
57 | #define SYS_CPUREG_T5 13 | ||
58 | #define SYS_CPUREG_T6 14 | ||
59 | #define SYS_CPUREG_T7 15 | ||
60 | #define SYS_CPUREG_S0 16 | ||
61 | #define SYS_CPUREG_S1 17 | ||
62 | #define SYS_CPUREG_S2 18 | ||
63 | #define SYS_CPUREG_S3 19 | ||
64 | #define SYS_CPUREG_S4 20 | ||
65 | #define SYS_CPUREG_S5 21 | ||
66 | #define SYS_CPUREG_S6 22 | ||
67 | #define SYS_CPUREG_S7 23 | ||
68 | #define SYS_CPUREG_T8 24 | ||
69 | #define SYS_CPUREG_T9 25 | ||
70 | #define SYS_CPUREG_K0 26 | ||
71 | #define SYS_CPUREG_K1 27 | ||
72 | #define SYS_CPUREG_GP 28 | ||
73 | #define SYS_CPUREG_SP 29 | ||
74 | #define SYS_CPUREG_S8 30 | ||
75 | #define SYS_CPUREG_FP SYS_CPUREG_S8 | ||
76 | #define SYS_CPUREG_RA 31 | ||
77 | |||
78 | |||
79 | /* CPU register fp ($30) has an alias s8 */ | ||
80 | #define s8 fp | ||
81 | |||
82 | |||
83 | /* Aliases for System Control Coprocessor (CP0) registers */ | ||
84 | #define C0_INDEX C0_Index | ||
85 | #define C0_RANDOM C0_Random | ||
86 | #define C0_ENTRYLO0 C0_EntryLo0 | ||
87 | #define C0_ENTRYLO1 C0_EntryLo1 | ||
88 | #define C0_CONTEXT C0_Context | ||
89 | #define C0_PAGEMASK C0_PageMask | ||
90 | #define C0_WIRED C0_Wired | ||
91 | #define C0_BADVADDR C0_BadVAddr | ||
92 | #define C0_COUNT C0_Count | ||
93 | #define C0_ENTRYHI C0_EntryHi | ||
94 | #define C0_COMPARE C0_Compare | ||
95 | #define C0_STATUS C0_Status | ||
96 | #define C0_CAUSE C0_Cause | ||
97 | |||
98 | #ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ | ||
99 | #undef C0_PRID | ||
100 | #endif | ||
101 | #define C0_PRID C0_PRId | ||
102 | |||
103 | #define C0_CONFIG C0_Config | ||
104 | #define C0_CONFIG1 C0_Config1 | ||
105 | #define C0_LLADDR C0_LLAddr | ||
106 | #define C0_WATCHLO C0_WatchLo | ||
107 | #define C0_WATCHHI C0_WatchHi | ||
108 | #define C0_DEBUG C0_Debug | ||
109 | #define C0_PERFCNT C0_PerfCnt | ||
110 | #define C0_ERRCTL C0_ErrCtl | ||
111 | #define C0_CACHEERR C0_CacheErr | ||
112 | #define C0_TAGLO C0_TagLo | ||
113 | #define C0_DATALO C0_DataLo | ||
114 | #define C0_TAGHI C0_TagHi | ||
115 | #define C0_DATAHI C0_DataHi | ||
116 | #define C0_ERROREPC C0_ErrorEPC | ||
117 | #if 0 | ||
118 | #define C0_DESAVE C0_DESAVE | ||
119 | #define C0_EPC C0_EPC | ||
120 | #define C0_DEPC C0_DEPC | ||
121 | #endif | ||
122 | |||
123 | /* System Control Coprocessor (CP0) registers select fields */ | ||
124 | #define C0_INDEX_SEL 0 /* TLB Index */ | ||
125 | #define C0_RANDOM_SEL 0 /* TLB Random */ | ||
126 | #define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ | ||
127 | #define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ | ||
128 | #define C0_CONTEXT_SEL 0 /* Context */ | ||
129 | #define C0_PAGEMASK_SEL 0 /* TLB PageMask */ | ||
130 | #define C0_WIRED_SEL 0 /* TLB Wired */ | ||
131 | #define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ | ||
132 | #define C0_COUNT_SEL 0 /* Count */ | ||
133 | #define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ | ||
134 | #define C0_COMPARE_SEL 0 /* Compare */ | ||
135 | #define C0_STATUS_SEL 0 /* Processor Status */ | ||
136 | #define C0_CAUSE_SEL 0 /* Exception Cause */ | ||
137 | #define C0_EPC_SEL 0 /* Exception PC */ | ||
138 | #define C0_PRID_SEL 0 /* Processor Revision Indentifier */ | ||
139 | #define C0_CONFIG_SEL 0 /* Config */ | ||
140 | #define C0_CONFIG1_SEL 1 /* Config1 */ | ||
141 | #define C0_LLADDR_SEL 0 /* LLAddr */ | ||
142 | #define C0_WATCHLO_SEL 0 /* WatchpointLo */ | ||
143 | #define C0_WATCHHI_SEL 0 /* WatchpointHi */ | ||
144 | #define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ | ||
145 | #define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ | ||
146 | #define C0_PERFCNT_SEL 0 /* Performance counter interface */ | ||
147 | #define C0_ERRCTL_SEL 0 /* ERRCTL */ | ||
148 | #define C0_CACHEERR_SEL 0 /* CacheErr */ | ||
149 | #define C0_TAGLO_SEL 0 /* TagLo */ | ||
150 | #define C0_DATALO_SEL 1 /* DataLo */ | ||
151 | #define C0_DTAGLO_SEL 2 /* DTagLo */ | ||
152 | #define C0_TAGHI_SEL 0 /* TagHi */ | ||
153 | #define C0_DATAHI_SEL 1 /* DataHi */ | ||
154 | #define C0_DTAGHI_SEL 2 /* DTagHi */ | ||
155 | #define C0_ERROREPC_SEL 0 /* ErrorEPC */ | ||
156 | #define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ | ||
157 | |||
158 | |||
159 | /* C0_CONFIG register encoding */ | ||
160 | |||
161 | #define C0_CONFIG_M_SHF S_ConfigMore | ||
162 | #define C0_CONFIG_M_MSK M_ConfigMore | ||
163 | #define C0_CONFIG_M_BIT C0_CONFIG_M_MSK | ||
164 | |||
165 | #define C0_CONFIG_BE_SHF S_ConfigBE | ||
166 | #define C0_CONFIG_BE_MSK M_ConfigBE | ||
167 | #define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK | ||
168 | |||
169 | #define C0_CONFIG_AT_SHF S_ConfigAT | ||
170 | #define C0_CONFIG_AT_MSK M_ConfigAT | ||
171 | #define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 | ||
172 | #define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S | ||
173 | #define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 | ||
174 | |||
175 | #define C0_CONFIG_AR_SHF S_ConfigAR | ||
176 | #define C0_CONFIG_AR_MSK M_ConfigAR | ||
177 | |||
178 | #define C0_CONFIG_MT_SHF S_ConfigMT | ||
179 | #define C0_CONFIG_MT_MSK M_ConfigMT | ||
180 | #define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU | ||
181 | #define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU | ||
182 | #define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU | ||
183 | #define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU | ||
184 | |||
185 | #define C0_CONFIG_K0_SHF S_ConfigK0 | ||
186 | #define C0_CONFIG_K0_MSK M_ConfigK0 | ||
187 | #define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA | ||
188 | #define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA | ||
189 | #define C0_CONFIG_K0_UNCACHED K_CacheAttrU | ||
190 | #define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN | ||
191 | #define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE | ||
192 | #define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS | ||
193 | #define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU | ||
194 | #define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA | ||
195 | |||
196 | |||
197 | /* WC field. | ||
198 | * | ||
199 | * This feature is present specifically to support configuration | ||
200 | * testing of the core in a lead vehicle, and is not supported | ||
201 | * in any other environment. Attempting to use this feature | ||
202 | * outside of the scope of a lead vehicle is a violation of the | ||
203 | * MIPS Architecture, and may cause unpredictable operation of | ||
204 | * the processor. | ||
205 | */ | ||
206 | #define C0_CONFIG_WC_SHF 19 | ||
207 | #define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) | ||
208 | #define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK | ||
209 | |||
210 | |||
211 | /* C0_CONFIG1 register encoding */ | ||
212 | |||
213 | #define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize | ||
214 | #define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize | ||
215 | |||
216 | #define C0_CONFIG1_IS_SHF S_Config1IS | ||
217 | #define C0_CONFIG1_IS_MSK M_Config1IS | ||
218 | |||
219 | #define C0_CONFIG1_IL_SHF S_Config1IL | ||
220 | #define C0_CONFIG1_IL_MSK M_Config1IL | ||
221 | |||
222 | #define C0_CONFIG1_IA_SHF S_Config1IA | ||
223 | #define C0_CONFIG1_IA_MSK M_Config1IA | ||
224 | |||
225 | #define C0_CONFIG1_DS_SHF S_Config1DS | ||
226 | #define C0_CONFIG1_DS_MSK M_Config1DS | ||
227 | |||
228 | #define C0_CONFIG1_DL_SHF S_Config1DL | ||
229 | #define C0_CONFIG1_DL_MSK M_Config1DL | ||
230 | |||
231 | #define C0_CONFIG1_DA_SHF S_Config1DA | ||
232 | #define C0_CONFIG1_DA_MSK M_Config1DA | ||
233 | |||
234 | #define C0_CONFIG1_WR_SHF S_Config1WR | ||
235 | #define C0_CONFIG1_WR_MSK M_Config1WR | ||
236 | #define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK | ||
237 | |||
238 | #define C0_CONFIG1_CA_SHF S_Config1CA | ||
239 | #define C0_CONFIG1_CA_MSK M_Config1CA | ||
240 | #define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK | ||
241 | |||
242 | #define C0_CONFIG1_EP_SHF S_Config1EP | ||
243 | #define C0_CONFIG1_EP_MSK M_Config1EP | ||
244 | #define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK | ||
245 | |||
246 | #define C0_CONFIG1_FP_SHF S_Config1FP | ||
247 | #define C0_CONFIG1_FP_MSK M_Config1FP | ||
248 | #define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK | ||
249 | |||
250 | |||
251 | /* C0_STATUS register encoding */ | ||
252 | |||
253 | #define C0_STATUS_CU3_SHF S_StatusCU3 | ||
254 | #define C0_STATUS_CU3_MSK M_StatusCU3 | ||
255 | #define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK | ||
256 | |||
257 | #define C0_STATUS_CU2_SHF S_StatusCU2 | ||
258 | #define C0_STATUS_CU2_MSK M_StatusCU2 | ||
259 | #define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK | ||
260 | |||
261 | #define C0_STATUS_CU1_SHF S_StatusCU1 | ||
262 | #define C0_STATUS_CU1_MSK M_StatusCU1 | ||
263 | #define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK | ||
264 | |||
265 | #define C0_STATUS_CU0_SHF S_StatusCU1 | ||
266 | #define C0_STATUS_CU0_MSK M_StatusCU1 | ||
267 | #define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK | ||
268 | |||
269 | #define C0_STATUS_RP_SHF S_StatusRP | ||
270 | #define C0_STATUS_RP_MSK M_StatusRP | ||
271 | #define C0_STATUS_RP_BIT C0_STATUS_RP_MSK | ||
272 | |||
273 | #define C0_STATUS_FR_SHF S_StatusFR | ||
274 | #define C0_STATUS_FR_MSK M_StatusFR | ||
275 | #define C0_STATUS_FR_BIT C0_STATUS_FR_MSK | ||
276 | |||
277 | #define C0_STATUS_RE_SHF S_StatusRE | ||
278 | #define C0_STATUS_RE_MSK M_StatusRE | ||
279 | #define C0_STATUS_RE_BIT C0_STATUS_RE_MSK | ||
280 | |||
281 | #define C0_STATUS_BEV_SHF S_StatusBEV | ||
282 | #define C0_STATUS_BEV_MSK M_StatusBEV | ||
283 | #define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK | ||
284 | |||
285 | #define C0_STATUS_TS_SHF S_StatusTS | ||
286 | #define C0_STATUS_TS_MSK M_StatusTS | ||
287 | #define C0_STATUS_TS_BIT C0_STATUS_TS_MSK | ||
288 | |||
289 | #define C0_STATUS_SR_SHF S_StatusSR | ||
290 | #define C0_STATUS_SR_MSK M_StatusSR | ||
291 | #define C0_STATUS_SR_BIT C0_STATUS_SR_MSK | ||
292 | |||
293 | #define C0_STATUS_NMI_SHF S_StatusNMI | ||
294 | #define C0_STATUS_NMI_MSK M_StatusNMI | ||
295 | #define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK | ||
296 | |||
297 | #define C0_STATUS_IM_SHF S_StatusIM | ||
298 | #define C0_STATUS_IM_MSK M_StatusIM | ||
299 | /* Note that the the definitions below indicate the interrupt number | ||
300 | * rather than the mask. | ||
301 | * (0..1 for SW interrupts and 2...7 for HW interrupts) | ||
302 | */ | ||
303 | #define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) | ||
304 | #define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) | ||
305 | #define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) | ||
306 | #define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) | ||
307 | #define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) | ||
308 | #define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) | ||
309 | #define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) | ||
310 | #define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) | ||
311 | |||
312 | /* Max interrupt code */ | ||
313 | #define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 | ||
314 | |||
315 | #define C0_STATUS_KSU_SHF S_StatusKSU | ||
316 | #define C0_STATUS_KSU_MSK M_StatusKSU | ||
317 | |||
318 | #define C0_STATUS_UM_SHF S_StatusUM | ||
319 | #define C0_STATUS_UM_MSK M_StatusUM | ||
320 | #define C0_STATUS_UM_BIT C0_STATUS_UM_MSK | ||
321 | |||
322 | #define C0_STATUS_ERL_SHF S_StatusERL | ||
323 | #define C0_STATUS_ERL_MSK M_StatusERL | ||
324 | #define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK | ||
325 | |||
326 | #define C0_STATUS_EXL_SHF S_StatusEXL | ||
327 | #define C0_STATUS_EXL_MSK M_StatusEXL | ||
328 | #define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK | ||
329 | |||
330 | #define C0_STATUS_IE_SHF S_StatusIE | ||
331 | #define C0_STATUS_IE_MSK M_StatusIE | ||
332 | #define C0_STATUS_IE_BIT C0_STATUS_IE_MSK | ||
333 | |||
334 | |||
335 | /* C0_PRID register encoding */ | ||
336 | |||
337 | #define C0_PRID_OPT_SHF S_PRIdCoOpt | ||
338 | #define C0_PRID_OPT_MSK M_PRIdCoOpt | ||
339 | |||
340 | #define C0_PRID_COMP_SHF S_PRIdCoID | ||
341 | #define C0_PRID_COMP_MSK M_PRIdCoID | ||
342 | #define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS | ||
343 | #define C0_PRID_COMP_NOT_MIPS32_64 0 | ||
344 | |||
345 | #define C0_PRID_PRID_SHF S_PRIdImp | ||
346 | #define C0_PRID_PRID_MSK M_PRIdImp | ||
347 | |||
348 | /* Jade */ | ||
349 | #define C0_PRID_PRID_4Kc K_PRIdImp_Jade | ||
350 | #define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ | ||
351 | /* Emerald */ | ||
352 | #define C0_PRID_PRID_4KEc K_PRIdImp_4KEc | ||
353 | #define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp | ||
354 | /* Coral */ | ||
355 | #define C0_PRID_PRID_4KSc K_PRIdImp_4KSc | ||
356 | /* Opal */ | ||
357 | #define C0_PRID_PRID_5K K_PRIdImp_Opal | ||
358 | /* Ruby */ | ||
359 | #define C0_PRID_PRID_20Kc K_PRIdImp_Ruby | ||
360 | /* Other CPUs */ | ||
361 | #define C0_PRID_PRID_R4000 K_PRIdImp_R4000 | ||
362 | #define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 | ||
363 | #define C0_PRID_PRID_RM70XX 0x27 | ||
364 | |||
365 | #define C0_PRID_REV_SHF S_PRIdRev | ||
366 | #define C0_PRID_REV_MSK M_PRIdRev | ||
367 | |||
368 | |||
369 | #define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ | ||
370 | C0_PRID_COMP_SHF) | \ | ||
371 | (C0_PRID_PRID_4Kc << \ | ||
372 | C0_PRID_PRID_SHF) \ | ||
373 | ) | ||
374 | |||
375 | #define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ | ||
376 | C0_PRID_COMP_SHF) | \ | ||
377 | (C0_PRID_PRID_4Kmp << \ | ||
378 | C0_PRID_PRID_SHF) \ | ||
379 | ) | ||
380 | |||
381 | #define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ | ||
382 | C0_PRID_COMP_SHF) | \ | ||
383 | (C0_PRID_PRID_4KEc << \ | ||
384 | C0_PRID_PRID_SHF) \ | ||
385 | ) | ||
386 | |||
387 | #define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ | ||
388 | C0_PRID_COMP_SHF) | \ | ||
389 | (C0_PRID_PRID_4KEmp << \ | ||
390 | C0_PRID_PRID_SHF) \ | ||
391 | ) | ||
392 | |||
393 | #define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ | ||
394 | C0_PRID_COMP_SHF) | \ | ||
395 | (C0_PRID_PRID_4KSc << \ | ||
396 | C0_PRID_PRID_SHF) \ | ||
397 | ) | ||
398 | |||
399 | #define MIPS_5K ( (C0_PRID_COMP_MIPS << \ | ||
400 | C0_PRID_COMP_SHF) | \ | ||
401 | (C0_PRID_PRID_5K << \ | ||
402 | C0_PRID_PRID_SHF) \ | ||
403 | ) | ||
404 | |||
405 | #define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ | ||
406 | C0_PRID_COMP_SHF) | \ | ||
407 | (C0_PRID_PRID_20Kc << \ | ||
408 | C0_PRID_PRID_SHF) \ | ||
409 | ) | ||
410 | |||
411 | #define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
412 | C0_PRID_COMP_SHF) | \ | ||
413 | (C0_PRID_PRID_RM52XX << \ | ||
414 | C0_PRID_PRID_SHF) \ | ||
415 | ) | ||
416 | |||
417 | #define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
418 | C0_PRID_COMP_SHF) | \ | ||
419 | (C0_PRID_PRID_RM70XX << \ | ||
420 | C0_PRID_PRID_SHF) \ | ||
421 | ) | ||
422 | |||
423 | /* C0_ENTRYHI register encoding */ | ||
424 | |||
425 | #define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 | ||
426 | #define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 | ||
427 | |||
428 | #define C0_ENTRYHI_ASID_SHF S_EntryHiASID | ||
429 | #define C0_ENTRYHI_ASID_MSK M_EntryHiASID | ||
430 | |||
431 | |||
432 | /* C0_CAUSE register encoding */ | ||
433 | |||
434 | #define C0_CAUSE_BD_SHF S_CauseBD | ||
435 | #define C0_CAUSE_BD_MSK M_CauseBD | ||
436 | #define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK | ||
437 | |||
438 | #define C0_CAUSE_CE_SHF S_CauseCE | ||
439 | #define C0_CAUSE_CE_MSK M_CauseCE | ||
440 | |||
441 | #define C0_CAUSE_IV_SHF S_CauseIV | ||
442 | #define C0_CAUSE_IV_MSK M_CauseIV | ||
443 | #define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK | ||
444 | |||
445 | #define C0_CAUSE_WP_SHF S_CauseWP | ||
446 | #define C0_CAUSE_WP_MSK M_CauseWP | ||
447 | #define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK | ||
448 | |||
449 | #define C0_CAUSE_IP_SHF S_CauseIP | ||
450 | #define C0_CAUSE_IP_MSK M_CauseIP | ||
451 | |||
452 | #define C0_CAUSE_CODE_SHF S_CauseExcCode | ||
453 | #define C0_CAUSE_CODE_MSK M_CauseExcCode | ||
454 | |||
455 | #define C0_CAUSE_CODE_INT EX_INT | ||
456 | #define C0_CAUSE_CODE_MOD EX_MOD | ||
457 | #define C0_CAUSE_CODE_TLBL EX_TLBL | ||
458 | #define C0_CAUSE_CODE_TLBS EX_TLBS | ||
459 | #define C0_CAUSE_CODE_ADEL EX_ADEL | ||
460 | #define C0_CAUSE_CODE_ADES EX_ADES | ||
461 | #define C0_CAUSE_CODE_IBE EX_IBE | ||
462 | #define C0_CAUSE_CODE_DBE EX_DBE | ||
463 | #define C0_CAUSE_CODE_SYS EX_SYS | ||
464 | #define C0_CAUSE_CODE_BP EX_BP | ||
465 | #define C0_CAUSE_CODE_RI EX_RI | ||
466 | #define C0_CAUSE_CODE_CPU EX_CPU | ||
467 | #define C0_CAUSE_CODE_OV EX_OV | ||
468 | #define C0_CAUSE_CODE_TR EV_TR | ||
469 | #define C0_CAUSE_CODE_FPE EX_FPE | ||
470 | #define C0_CAUSE_CODE_WATCH EX_WATCH | ||
471 | #define C0_CAUSE_CODE_MCHECK EX_MCHECK | ||
472 | |||
473 | /* Max cause code */ | ||
474 | #define C0_CAUSE_CODE_MAX EX_MCHECK | ||
475 | |||
476 | |||
477 | /* C0_PAGEMASK register encoding */ | ||
478 | #define C0_PAGEMASK_MASK_SHF S_PageMaskMask | ||
479 | #define C0_PAGEMASK_MASK_MSK M_PageMaskMask | ||
480 | #define C0_PAGEMASK_MASK_4K K_PageMask4K | ||
481 | #define C0_PAGEMASK_MASK_16K K_PageMask16K | ||
482 | #define C0_PAGEMASK_MASK_64K K_PageMask64K | ||
483 | #define C0_PAGEMASK_MASK_256K K_PageMask256K | ||
484 | #define C0_PAGEMASK_MASK_1M K_PageMask1M | ||
485 | #define C0_PAGEMASK_MASK_4M K_PageMask4M | ||
486 | #define C0_PAGEMASK_MASK_16M K_PageMask16M | ||
487 | |||
488 | |||
489 | /* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ | ||
490 | #define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN | ||
491 | #define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN | ||
492 | |||
493 | #define C0_ENTRYLO0_C_SHF S_EntryLoC | ||
494 | #define C0_ENTRYLO0_C_MSK M_EntryLoC | ||
495 | |||
496 | #define C0_ENTRYLO0_D_SHF S_EntryLoD | ||
497 | #define C0_ENTRYLO0_D_MSK M_EntryLoD | ||
498 | |||
499 | #define C0_ENTRYLO0_V_SHF S_EntryLoV | ||
500 | #define C0_ENTRYLO0_V_MSK M_EntryLoV | ||
501 | |||
502 | #define C0_ENTRYLO0_G_SHF S_EntryLoG | ||
503 | #define C0_ENTRYLO0_G_MSK M_EntryLoG | ||
504 | |||
505 | |||
506 | /* FPU (CP1) FIR register encoding */ | ||
507 | #define C1_FIR_3D_SHF S_FIRConfig3D | ||
508 | #define C1_FIR_3D_MSK M_FIRConfig3D | ||
509 | |||
510 | #define C1_FIR_PS_SHF S_FIRConfigPS | ||
511 | #define C1_FIR_PS_MSK M_FIRConfigPS | ||
512 | |||
513 | #define C1_FIR_D_SHF S_FIRConfigD | ||
514 | #define C1_FIR_D_MSK M_FIRConfigD | ||
515 | |||
516 | #define C1_FIR_S_SHF S_FIRConfigS | ||
517 | #define C1_FIR_S_MSK M_FIRConfigS | ||
518 | |||
519 | #define C1_FIR_PRID_SHF S_FIRImp | ||
520 | #define C1_FIR_PRID_MSK M_FIRImp | ||
521 | |||
522 | #define C1_FIR_REV_SHF S_FIRRev | ||
523 | #define C1_FIR_REV_MSK M_FIRRev | ||
524 | |||
525 | |||
526 | /* FPU (CP1) FCSR control/status register */ | ||
527 | #define C1_FCSR_FCC_SHF S_FCSRFCC7_1 | ||
528 | #define C1_FCSR_FCC_MSK M_FCSRFCC7_1 | ||
529 | |||
530 | #define C1_FCSR_FS_SHF S_FCSRFS | ||
531 | #define C1_FCSR_FS_MSK M_FCSRFS | ||
532 | #define C1_FCSR_FS_BIT C1_FCSR_FS_MSK | ||
533 | |||
534 | #define C1_FCSR_CC_SHF S_FCSRCC | ||
535 | #define C1_FCSR_CC_MSK M_FCSRCC | ||
536 | |||
537 | #define C1_FCSR_IMPL_SHF S_FCSRImpl | ||
538 | #define C1_FCSR_IMPL_MSK M_FCSRImpl | ||
539 | |||
540 | #define C1_FCSR_EXC_SHF S_FCSRExc | ||
541 | #define C1_FCSR_EXC_MSK M_FCSRExc | ||
542 | |||
543 | #define C1_FCSR_ENA_SHF S_FCSREna | ||
544 | #define C1_FCSR_ENA_MSK M_FCSREna | ||
545 | |||
546 | #define C1_FCSR_FLG_SHF S_FCSRFlg | ||
547 | #define C1_FCSR_FLG_MSK M_FCSRFlg | ||
548 | |||
549 | #define C1_FCSR_RM_SHF S_FCSRRM | ||
550 | #define C1_FCSR_RM_MSK M_FCSRRM | ||
551 | #define C1_FCSR_RM_RN K_FCSRRM_RN | ||
552 | #define C1_FCSR_RM_RZ K_FCSRRM_RZ | ||
553 | #define C1_FCSR_RM_RP K_FCSRRM_RP | ||
554 | #define C1_FCSR_RM_RM K_FCSRRM_RM | ||
555 | |||
556 | |||
557 | |||
558 | /* cache operations */ | ||
559 | |||
560 | #define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) | ||
561 | |||
562 | #define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) | ||
563 | #define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) | ||
564 | #define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) | ||
565 | #define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) | ||
566 | #define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) | ||
567 | #define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) | ||
568 | #define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) | ||
569 | |||
570 | #define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) | ||
571 | #define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) | ||
572 | #define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) | ||
573 | #define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) | ||
574 | #define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) | ||
575 | #define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) | ||
576 | #define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) | ||
577 | |||
578 | #define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) | ||
579 | |||
580 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
581 | * processors. Only relevant in early engineering samples of test | ||
582 | * chips (RTL revision <= 3.0). | ||
583 | * | ||
584 | * The bug is described in : | ||
585 | * | ||
586 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
587 | * MIPS Document No: MD00003 | ||
588 | * | ||
589 | * The bug is identified as : C16 | ||
590 | */ | ||
591 | #ifndef SET_MIPS0 | ||
592 | #define SET_MIPS0() | ||
593 | #define SET_PUSH() | ||
594 | #define SET_POP() | ||
595 | #endif | ||
596 | #define ICACHE_INVALIDATE_WORKAROUND(reg) \ | ||
597 | SET_PUSH(); \ | ||
598 | SET_MIPS0(); \ | ||
599 | la reg, 999f; \ | ||
600 | SET_POP(); \ | ||
601 | cache ICACHE_ADDR_FILL, 0(reg); \ | ||
602 | sync; \ | ||
603 | nop; nop; nop; nop; \ | ||
604 | 999: | ||
605 | |||
606 | /* EMPTY_PIPELINE is used for the below cache invalidation operations. | ||
607 | * When $I is invalidated, there will still be operations in the | ||
608 | * pipeline. We make sure these are 'nop' operations. | ||
609 | */ | ||
610 | #define EMPTY_PIPELINE nop; nop; nop; nop | ||
611 | |||
612 | #define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ | ||
613 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
614 | cache ICACHE_INDEX_INVALIDATE, 0(index); \ | ||
615 | EMPTY_PIPELINE | ||
616 | |||
617 | #define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ | ||
618 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
619 | cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ | ||
620 | EMPTY_PIPELINE | ||
621 | |||
622 | /* The sync used in the below macro is there in case we are installing | ||
623 | * a new instruction (flush $D, sync, invalidate $I sequence). | ||
624 | */ | ||
625 | #define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ | ||
626 | cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ | ||
627 | sync; \ | ||
628 | EMPTY_PIPELINE | ||
629 | |||
630 | /* Config1 cache field decoding */ | ||
631 | #define CACHE_CALC_SPW(s) ( 64 << (s) ) | ||
632 | #define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) | ||
633 | #define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) | ||
634 | #define CACHE_CALC_ASSOC(a) ( (a) + 1 ) | ||
635 | |||
636 | |||
637 | /**** Move from/to Coprocessor operations ****/ | ||
638 | |||
639 | /* We use ssnop instead of nop operations in order to handle | ||
640 | * superscalar CPUs. | ||
641 | * The "sll zero,zero,1" notation is compiler backwards compatible. | ||
642 | */ | ||
643 | #define SSNOP sll zero,zero,1 | ||
644 | #define NOPS SSNOP; SSNOP; SSNOP; SSNOP | ||
645 | |||
646 | #define MFLO(dst) \ | ||
647 | mflo dst;\ | ||
648 | NOPS | ||
649 | |||
650 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
651 | * processors. | ||
652 | * | ||
653 | * This concerns the nop instruction before mtc0 in the | ||
654 | * MTC0 macro below. | ||
655 | * | ||
656 | * The bug is described in : | ||
657 | * | ||
658 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
659 | * MIPS Document No: MD00003 | ||
660 | * | ||
661 | * The bug is identified as : C27 | ||
662 | */ | ||
663 | |||
664 | #define MTC0(src, dst) \ | ||
665 | nop; \ | ||
666 | mtc0 src,dst;\ | ||
667 | NOPS | ||
668 | |||
669 | #define DMTC0(src, dst) \ | ||
670 | nop; \ | ||
671 | dmtc0 src,dst;\ | ||
672 | NOPS | ||
673 | |||
674 | #define MFC0(dst, src) \ | ||
675 | mfc0 dst,src;\ | ||
676 | NOPS | ||
677 | |||
678 | #define DMFC0(dst, src) \ | ||
679 | dmfc0 dst,src;\ | ||
680 | NOPS | ||
681 | |||
682 | #define MFC0_SEL_OPCODE(dst, src, sel)\ | ||
683 | .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
684 | NOPS | ||
685 | |||
686 | #define MTC0_SEL_OPCODE(dst, src, sel)\ | ||
687 | .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
688 | NOPS | ||
689 | |||
690 | #define LDC1(dst, src, offs)\ | ||
691 | .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) | ||
692 | |||
693 | #define SDC1(src, dst, offs)\ | ||
694 | .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) | ||
695 | |||
696 | |||
697 | /* Instruction opcode fields */ | ||
698 | #define OPC_SPECIAL 0x0 | ||
699 | #define OPC_REGIM 0x1 | ||
700 | #define OPC_J 0x2 | ||
701 | #define OPC_JAL 0x3 | ||
702 | #define OPC_BEQ 0x4 | ||
703 | #define OPC_BNE 0x5 | ||
704 | #define OPC_BLEZ 0x6 | ||
705 | #define OPC_BGTZ 0x7 | ||
706 | #define OPC_COP1 0x11 | ||
707 | #define OPC_JALX 0x1D | ||
708 | #define OPC_BEQL 0x14 | ||
709 | #define OPC_BNEL 0x15 | ||
710 | #define OPC_BLEZL 0x16 | ||
711 | #define OPC_BGTZL 0x17 | ||
712 | |||
713 | /* Instruction function fields */ | ||
714 | #define FUNC_JR 0x8 | ||
715 | #define FUNC_JALR 0x9 | ||
716 | |||
717 | /* Instruction rt fields */ | ||
718 | #define RT_BLTZ 0x0 | ||
719 | #define RT_BGEZ 0x1 | ||
720 | #define RT_BLTZL 0x2 | ||
721 | #define RT_BGEZL 0x3 | ||
722 | #define RT_BLTZAL 0x10 | ||
723 | #define RT_BGEZAL 0x11 | ||
724 | #define RT_BLTZALL 0x12 | ||
725 | #define RT_BGEZALL 0x13 | ||
726 | |||
727 | /* Instruction rs fields */ | ||
728 | #define RS_BC1 0x08 | ||
729 | |||
730 | /* Access macros for instruction fields */ | ||
731 | #define MIPS_OPCODE( instr) ((instr) >> 26) | ||
732 | #define MIPS_FUNCTION(instr) ((instr) & MSK(6)) | ||
733 | #define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) | ||
734 | #define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) | ||
735 | #define MIPS_OFFSET(instr) ((instr) & 0xFFFF) | ||
736 | #define MIPS_TARGET(instr) ((instr) & MSK(26)) | ||
737 | |||
738 | /* Instructions */ | ||
739 | #define OPCODE_DERET 0x4200001f | ||
740 | #define OPCODE_BREAK 0x0005000d | ||
741 | #define OPCODE_NOP 0 | ||
742 | #define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) | ||
743 | |||
744 | #define DERET .##word OPCODE_DERET | ||
745 | |||
746 | /* MIPS16e opcodes and instruction field access macros */ | ||
747 | |||
748 | #define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) | ||
749 | #define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) | ||
750 | #define MIPS16E_X(inst) (((inst) >> 26) & 0x1) | ||
751 | #define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) | ||
752 | #define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) | ||
753 | #define MIPS16E_OPC_EXTEND 0x1e | ||
754 | #define MIPS16E_OPC_JAL_X 0x03 | ||
755 | #define MIPS16E_OPC_B 0x02 | ||
756 | #define MIPS16E_OPC_BEQZ 0x04 | ||
757 | #define MIPS16E_OPC_BNEZ 0x05 | ||
758 | #define MIPS16E_OPC_I8 0x0c | ||
759 | #define MIPS16E_I8_FUNC_BTEQZ 0x00 | ||
760 | #define MIPS16E_I8_FUNC_BTNEZ 0x01 | ||
761 | #define MIPS16E_X_JALX 0x01 | ||
762 | #define MIPS16E_OPC_RR 0x1d | ||
763 | #define MIPS16E_RR_FUNC_JALRC 0x00 | ||
764 | #define MIPS16E_RR_RY_JRRX 0x00 | ||
765 | #define MIPS16E_RR_RY_JRRA 0x01 | ||
766 | #define MIPS16E_RR_RY_JALR 0x02 | ||
767 | #define MIPS16E_RR_RY_JRCRX 0x04 | ||
768 | #define MIPS16E_RR_RY_JRCRA 0x05 | ||
769 | #define MIPS16E_RR_RY_JALRC 0x06 | ||
770 | |||
771 | #define MIPS16E_OPCODE_BREAK 0xE805 | ||
772 | #define MIPS16E_OPCODE_NOP 0x6500 | ||
773 | |||
774 | /* MIPS reset vector */ | ||
775 | #define MIPS_RESET_VECTOR 0x1fc00000 | ||
776 | |||
777 | /* Clock periods per count register increment */ | ||
778 | #define MIPS4K_COUNT_CLK_PER_CYCLE 2 | ||
779 | #define MIPS5K_COUNT_CLK_PER_CYCLE 2 | ||
780 | #define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 | ||
781 | |||
782 | |||
783 | /**** MIPS 4K/5K families specific fields of CONFIG register ****/ | ||
784 | |||
785 | #define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23 | ||
786 | #define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF) | ||
787 | |||
788 | #define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU | ||
789 | #define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF) | ||
790 | |||
791 | |||
792 | /**** MIPS 20Kc specific fields of CONFIG register ****/ | ||
793 | |||
794 | #define C0_CONFIG_MIPS20KC_EC_SHF 28 | ||
795 | #define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF) | ||
796 | |||
797 | #define C0_CONFIG_MIPS20KC_DD_SHF 27 | ||
798 | #define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF) | ||
799 | #define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK | ||
800 | |||
801 | #define C0_CONFIG_MIPS20KC_LP_SHF 26 | ||
802 | #define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF) | ||
803 | #define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK | ||
804 | |||
805 | #define C0_CONFIG_MIPS20KC_SP_SHF 25 | ||
806 | #define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF) | ||
807 | #define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK | ||
808 | |||
809 | #define C0_CONFIG_MIPS20KC_TI_SHF 24 | ||
810 | #define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF) | ||
811 | #define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK | ||
812 | |||
813 | |||
814 | /* ********************************************************************* */ | ||
815 | /* Interface function definition */ | ||
816 | |||
817 | |||
818 | /* ********************************************************************* */ | ||
819 | |||
820 | #endif /* #ifndef __MIPS_H__ */ | ||