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authorMarcin Bukat <marcin.bukat@gmail.com>2010-10-31 21:09:34 +0000
committerMarcin Bukat <marcin.bukat@gmail.com>2010-10-31 21:09:34 +0000
commit56c4e9fa600557242d8b78f5fd8e32c2245b76fc (patch)
treef8558778a302f89c3e819e66e86577a5e37c3660 /firmware/export/mas.h
parent40ed5f57d9be61f1200026e9b0f944a9718111c1 (diff)
downloadrockbox-56c4e9fa600557242d8b78f5fd8e32c2245b76fc.tar.gz
rockbox-56c4e9fa600557242d8b78f5fd8e32c2245b76fc.zip
Separate mas35xx lowlevel stuff. Move SH specific bits to target tree. FS#11189 by me.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28425 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export/mas.h')
-rw-r--r--firmware/export/mas.h184
1 files changed, 0 insertions, 184 deletions
diff --git a/firmware/export/mas.h b/firmware/export/mas.h
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--- a/firmware/export/mas.h
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef _MAS_H_
22#define _MAS_H_
23
24#define MAS_BANK_D0 0
25#define MAS_BANK_D1 1
26
27#define MAX_PEAK 0x8000
28
29/*
30 MAS I2C defs
31*/
32#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
33#define MAS_ADR 0x3c
34#define MAS_DEV_WRITE (MAS_ADR | 0x00)
35#define MAS_DEV_READ (MAS_ADR | 0x01)
36
37#elif CONFIG_CODEC == MAS3507D
38#define MAS_ADR 0x3a
39#define MAS_DEV_WRITE (MAS_ADR | 0x00)
40#define MAS_DEV_READ (MAS_ADR | 0x01)
41#endif
42
43/* registers..*/
44#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
45#define MAS_DATA_WRITE 0x68
46#define MAS_DATA_READ 0x69
47#define MAS_CODEC_WRITE 0x6c
48#define MAS_CODEC_READ 0x6d
49#define MAS_CONTROL 0x6a
50#define MAS_DCCF 0x76
51#define MAS_DCFR 0x77
52
53#elif CONFIG_CODEC == MAS3507D
54#define MAS_DATA_WRITE 0x68
55#define MAS_DATA_READ 0x69
56#define MAS_CONTROL 0x6a
57#endif
58
59/*
60 * MAS register
61 */
62#define MAS_REG_DCCF 0x8e
63#define MAS_REG_MUTE 0xaa
64#define MAS_REG_PIODATA 0xc8
65#define MAS_REG_StartUpConfig 0xe6
66#define MAS_REG_KPRESCALE 0xe7
67#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
68#define MAS_REG_KMDB_SWITCH 0x21
69#define MAS_REG_KMDB_STR 0x22
70#define MAS_REG_KMDB_HAR 0x23
71#define MAS_REG_KMDB_FC 0x24
72#define MAS_REG_KLOUDNESS 0x1e
73#define MAS_REG_QPEAK_L 0x0a
74#define MAS_REG_QPEAK_R 0x0b
75#define MAS_REG_DQPEAK_L 0x0c
76#define MAS_REG_DQPEAK_R 0x0d
77#define MAS_REG_VOLUME_CONTROL 0x10
78#define MAS_REG_BALANCE 0x11
79#define MAS_REG_KAVC 0x12
80#define MAS_REG_KBASS 0x14
81#define MAS_REG_KTREBLE 0x15
82
83#elif CONFIG_CODEC == MAS3507D
84#define MAS_REG_KBASS 0x6b
85#define MAS_REG_KTREBLE 0x6f
86#endif
87
88/*
89 * MAS commands
90 */
91#if (CONFIG_CODEC == MAS3587F) || (CONFIG_CODEC == MAS3539F)
92#define MAS_CMD_READ_ANCILLARY 0x50
93#define MAS_CMD_FAST_PRG_DL 0x60
94#define MAS_CMD_READ_IC_VER 0x70
95#define MAS_CMD_READ_REG 0xa0
96#define MAS_CMD_WRITE_REG 0xb0
97#define MAS_CMD_READ_D0_MEM 0xc0
98#define MAS_CMD_READ_D1_MEM 0xd0
99#define MAS_CMD_WRITE_D0_MEM 0xe0
100#define MAS_CMD_WRITE_D1_MEM 0xf0
101
102#elif CONFIG_CODEC == MAS3507D
103#define MAS_CMD_READ_ANCILLARY 0x30
104#define MAS_CMD_WRITE_REG 0x90
105#define MAS_CMD_WRITE_D0_MEM 0xa0
106#define MAS_CMD_WRITE_D1_MEM 0xb0
107#define MAS_CMD_READ_REG 0xd0
108#define MAS_CMD_READ_D0_MEM 0xe0
109#define MAS_CMD_READ_D1_MEM 0xf0
110#endif
111
112/*
113 * MAS D0 memory cells (MAS3587F / MAS3539F)
114 */
115#if CONFIG_CODEC == MAS3587F
116#define MAS_D0_APP_SELECT 0x7f6
117#define MAS_D0_APP_RUNNING 0x7f7
118#define MAS_D0_ENCODER_CONTROL 0x7f0
119#define MAS_D0_IO_CONTROL_MAIN 0x7f1
120#define MAS_D0_INTERFACE_CONTROL 0x7f2
121#define MAS_D0_OFREQ_CONTROL 0x7f3
122#define MAS_D0_OUT_CLK_CONFIG 0x7f4
123#define MAS_D0_SPD_OUT_BITS 0x7f8
124#define MAS_D0_SOFT_MUTE 0x7f9
125#define MAS_D0_OUT_LL 0x7fc
126#define MAS_D0_OUT_LR 0x7fd
127#define MAS_D0_OUT_RL 0x7fe
128#define MAS_D0_OUT_RR 0x7ff
129#define MAS_D0_MPEG_FRAME_COUNT 0xfd0
130#define MAS_D0_MPEG_STATUS_1 0xfd1
131#define MAS_D0_MPEG_STATUS_2 0xfd2
132#define MAS_D0_CRC_ERROR_COUNT 0xfd3
133
134#elif CONFIG_CODEC == MAS3539F
135#define MAS_D0_APP_SELECT 0x34b
136#define MAS_D0_APP_RUNNING 0x34c
137/* no encoder :( */
138#define MAS_D0_IO_CONTROL_MAIN 0x346
139#define MAS_D0_INTERFACE_CONTROL 0x347
140#define MAS_D0_OFREQ_CONTROL 0x348
141#define MAS_D0_OUT_CLK_CONFIG 0x349
142#define MAS_D0_SPD_OUT_BITS 0x351
143#define MAS_D0_SOFT_MUTE 0x350
144#define MAS_D0_OUT_LL 0x354
145#define MAS_D0_OUT_LR 0x355
146#define MAS_D0_OUT_RL 0x356
147#define MAS_D0_OUT_RR 0x357
148#define MAS_D0_MPEG_FRAME_COUNT 0xfd0
149#define MAS_D0_MPEG_STATUS_1 0xfd1
150#define MAS_D0_MPEG_STATUS_2 0xfd2
151#define MAS_D0_CRC_ERROR_COUNT 0xfd3
152
153#elif CONFIG_CODEC == MAS3507D
154#define MAS_D0_MPEG_FRAME_COUNT 0x300
155#define MAS_D0_MPEG_STATUS_1 0x301
156#define MAS_D0_MPEG_STATUS_2 0x302
157#define MAS_D0_CRC_ERROR_COUNT 0x303
158#define MAS_D0_OUT_LL 0x7f8
159#define MAS_D0_OUT_LR 0x7f9
160#define MAS_D0_OUT_RL 0x7fa
161#define MAS_D0_OUT_RR 0x7fb
162
163#endif
164
165int mas_default_read(unsigned short *buf);
166int mas_run(unsigned short address);
167int mas_readmem(int bank, int addr, unsigned long* dest, int len);
168int mas_writemem(int bank, int addr, const unsigned long* src, int len);
169int mas_readreg(int reg);
170int mas_writereg(int reg, unsigned int val);
171void mas_reset(void);
172int mas_direct_config_read(unsigned char reg);
173int mas_direct_config_write(unsigned char reg, unsigned int val);
174int mas_codec_writereg(int reg, unsigned int val);
175int mas_codec_readreg(int reg);
176unsigned long mas_readver(void);
177
178#endif
179
180#if CONFIG_TUNER & S1A0903X01
181void mas_store_pllfreq(int freq);
182int mas_get_pllfreq(void);
183#endif
184
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