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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-23 17:30:58 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-07-13 22:01:33 +0100 |
commit | 4c60bc9e681865fcfc149775a1ed7ccd2613d5bf (patch) | |
tree | 99f8d91af2c171cf3843f0c14d41a20d9dc29c4f /firmware/export/es9218.h | |
parent | 3abb7c5dd5be2ec6744bfc0a80967b20f1b59e30 (diff) | |
download | rockbox-4c60bc9e681865fcfc149775a1ed7ccd2613d5bf.tar.gz rockbox-4c60bc9e681865fcfc149775a1ed7ccd2613d5bf.zip |
New port: Shanling Q1 native
- Audio playback works
- Touchscreen and buttons work
- Bootloader works and is capable of dual boot
- Plugins are working
- Cabbiev2 theme has been ported
- Stable for general usage
Thanks to Marc Aarts for porting Cabbiev2 and plugin bitmaps.
There's a few minor known issues:
- Bootloader must be installed manually using 'usbboot' as there is
no support in jztool yet.
- Keymaps may be lacking, need further testing and feedback.
- Some plugins may not be fully adapted to the screen size and could
benefit from further tweaking.
- LCD shows abnormal effects under some circumstances: for example,
after viewing a mostly black screen an afterimage appears briefly
when going back to a brightly-lit screen. Sudden power-off without
proper shutdown of the backlight causes a "dissolving" effect.
- CW2015 battery reporting driver is buggy, and disabled for now.
Battery reporting is currently voltage-based using the AXP192.
Change-Id: I635e83f02a880192c5a82cb0861ad3a61c137c3a
Diffstat (limited to 'firmware/export/es9218.h')
-rw-r--r-- | firmware/export/es9218.h | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/firmware/export/es9218.h b/firmware/export/es9218.h new file mode 100644 index 0000000000..1492304c67 --- /dev/null +++ b/firmware/export/es9218.h | |||
@@ -0,0 +1,230 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __ES9218_H__ | ||
23 | #define __ES9218_H__ | ||
24 | |||
25 | #include <stdbool.h> | ||
26 | #include <stdint.h> | ||
27 | |||
28 | #define AUDIOHW_CAPS (FILTER_ROLL_OFF_CAP|POWER_MODE_CAP) | ||
29 | #define AUDIOHW_HAVE_ES9218_ROLL_OFF | ||
30 | |||
31 | #define ES9218_DIG_VOLUME_MIN (-1275) | ||
32 | #define ES9218_DIG_VOLUME_MAX 0 | ||
33 | #define ES9218_DIG_VOLUME_STEP 5 | ||
34 | |||
35 | #define ES9218_AMP_VOLUME_MIN (-240) | ||
36 | #define ES9218_AMP_VOLUME_MAX 0 | ||
37 | #define ES9218_AMP_VOLUME_STEP 10 | ||
38 | |||
39 | AUDIOHW_SETTING(VOLUME, "dB", 1, ES9218_DIG_VOLUME_STEP, | ||
40 | ES9218_DIG_VOLUME_MIN, ES9218_DIG_VOLUME_MAX, -200) | ||
41 | AUDIOHW_SETTING(FILTER_ROLL_OFF, "", 0, 1, 0, 7, 0) | ||
42 | AUDIOHW_SETTING(POWER_MODE, "", 0, 1, 0, 1, 0) | ||
43 | |||
44 | /* Register addresses */ | ||
45 | #define ES9218_REG_SYSTEM 0x00 | ||
46 | #define ES9218_REG_INPUT_SEL 0x01 | ||
47 | #define ES9218_REG_MIX_AUTOMUTE 0x02 | ||
48 | #define ES9218_REG_ANALOG_VOL 0x03 | ||
49 | #define ES9218_REG_AUTOMUTE_TIME 0x04 | ||
50 | #define ES9218_REG_AUTOMUTE_LEVEL 0x05 | ||
51 | #define ES9218_REG_DOP_VOLUME_RAMP 0x06 | ||
52 | #define ES9218_REG_FILTER_SYS_MUTE 0x07 | ||
53 | #define ES9218_REG_GPIO1_2_CONFIG 0x08 | ||
54 | #define ES9218_REG_RESERVED_1 0x09 | ||
55 | #define ES9218_REG_MASTER_MODE_CONFIG 0x0a | ||
56 | #define ES9218_REG_OVERCURRENT_PROT 0x0b | ||
57 | #define ES9218_REG_ASRC_DPLL_BANDWIDTH 0x0c | ||
58 | #define ES9218_REG_THD_COMP_BYPASS 0x0d | ||
59 | #define ES9218_REG_SOFT_START_CONFIG 0x0e | ||
60 | #define ES9218_REG_VOLUME_LEFT 0x0f | ||
61 | #define ES9218_REG_VOLUME_RIGHT 0x10 | ||
62 | #define ES9218_REG_MASTER_TRIM_BIT0_7 0x11 | ||
63 | #define ES9218_REG_MASTER_TRIM_BIT8_15 0x12 | ||
64 | #define ES9218_REG_MASTER_TRIM_BIT16_23 0x13 | ||
65 | #define ES9218_REG_MASTER_TRIM_BIT24_31 0x14 | ||
66 | #define ES9218_REG_GPIO_INPUT_SEL 0x15 | ||
67 | #define ES9218_REG_THD_COMP_C2_LO 0x16 | ||
68 | #define ES9218_REG_THD_COMP_C2_HI 0x17 | ||
69 | #define ES9218_REG_THD_COMP_C3_LO 0x18 | ||
70 | #define ES9218_REG_THD_COMP_C3_HI 0x19 | ||
71 | #define ES9218_REG_CHARGE_PUMP_SS_DELAY 0x1a | ||
72 | #define ES9218_REG_GENERAL_CONFIG 0x1b | ||
73 | #define ES9218_REG_RESERVED_2 0x1c | ||
74 | #define ES9218_REG_GPIO_INV_CLOCK_GEAR 0x1d | ||
75 | #define ES9218_REG_CHARGE_PUMP_CLK_LO 0x1e | ||
76 | #define ES9218_REG_CHARGE_PUMP_CLK_HI 0x1f | ||
77 | #define ES9218_REG_AMP_CONFIG 0x20 | ||
78 | #define ES9218_REG_INTERRUPT_MASK 0x21 | ||
79 | #define ES9218_REG_PROG_NCO_BIT0_7 0x22 | ||
80 | #define ES9218_REG_PROG_NCO_BIT8_15 0x23 | ||
81 | #define ES9218_REG_PROG_NCO_BIT16_23 0x24 | ||
82 | #define ES9218_REG_PROG_NCO_BIT24_31 0x25 | ||
83 | #define ES9218_REG_RESERVED_3 0x27 | ||
84 | #define ES9218_REG_FIR_RAM_ADDR 0x28 | ||
85 | #define ES9218_REG_FIR_DATA_BIT0_7 0x29 | ||
86 | #define ES9218_REG_FIR_DATA_BIT8_15 0x2a | ||
87 | #define ES9218_REG_FIR_DATA_BIT16_23 0x2b | ||
88 | #define ES9218_REG_PROG_FIR_CONFIG 0x2c | ||
89 | #define ES9218_REG_ANALOG_OVERRIDE_1 0x2d | ||
90 | #define ES9218_REG_ANALOG_OVERRIDE_2 0x2e | ||
91 | #define ES9218_REG_ANALOG_OVERRIDE_3 0x2f | ||
92 | #define ES9218_REG_ANALOG_CTRL 0x30 | ||
93 | #define ES9218_REG_CLKGEAR_CFG_BIT0_7 0x31 | ||
94 | #define ES9218_REG_CLKGEAR_CFG_BIT8_15 0x32 | ||
95 | #define ES9218_REG_CLKGEAR_CFG_BIT16_23 0x33 | ||
96 | #define ES9218_REG_RESERVED_4 0x34 | ||
97 | #define ES9218_REG_THD_COMP_C2_CH2_LO 0x35 | ||
98 | #define ES9218_REG_THD_COMP_C2_CH2_HI 0x36 | ||
99 | #define ES9218_REG_THD_COMP_C3_CH2_LO 0x37 | ||
100 | #define ES9218_REG_THD_COMP_C3_CH2_HI 0x38 | ||
101 | #define ES9218_REG_RESERVED_5 0x39 | ||
102 | #define ES9218_REG_RESERVED_6 0x3a | ||
103 | #define ES9218_REG_RESERVED_7 0x3b | ||
104 | #define ES9218_REG_RESERVED_8 0x3c | ||
105 | #define ES9218_REG_CHIP_ID_AND_STATUS 0x40 | ||
106 | #define ES9218_REG_GPIO_AND_CLOCK_GEAR 0x41 | ||
107 | #define ES9218_REG_DPLL_NUMBER_BIT0_7 0x42 | ||
108 | #define ES9218_REG_DPLL_NUMBER_BIT8_15 0x43 | ||
109 | #define ES9218_REG_DPLL_NUMBER_BIT16_23 0x44 | ||
110 | #define ES9218_REG_DPLL_NUMBER_BIT24_31 0x45 | ||
111 | #define ES9218_REG_INPUT_MUTE_STATUS 0x48 | ||
112 | #define ES9218_REG_FIR_READ_BIT0_7 0x49 | ||
113 | #define ES9218_REG_FIR_READ_BIT8_15 0x4a | ||
114 | #define ES9218_REG_FIR_READ_BIT16_23 0x4b | ||
115 | |||
116 | enum es9218_clock_gear { | ||
117 | ES9218_CLK_GEAR_1 = 0, /* CLK = XI/1 */ | ||
118 | ES9218_CLK_GEAR_2 = 1, /* CLK = XI/2 */ | ||
119 | ES9218_CLK_GEAR_4 = 2, /* CLK = XI/4 */ | ||
120 | ES9218_CLK_GEAR_8 = 3, /* CLK = XI/8 */ | ||
121 | }; | ||
122 | |||
123 | enum es9218_amp_mode { | ||
124 | ES9218_AMP_MODE_CORE_ON = 0, | ||
125 | ES9218_AMP_MODE_LOWFI = 1, | ||
126 | ES9218_AMP_MODE_1VRMS = 2, | ||
127 | ES9218_AMP_MODE_2VRMS = 3, | ||
128 | }; | ||
129 | |||
130 | enum es9218_iface_role { | ||
131 | ES9218_IFACE_ROLE_SLAVE = 0, | ||
132 | ES9218_IFACE_ROLE_MASTER = 1, | ||
133 | }; | ||
134 | |||
135 | enum es9218_iface_format { | ||
136 | ES9218_IFACE_FORMAT_I2S = 0, | ||
137 | ES9218_IFACE_FORMAT_LJUST = 1, | ||
138 | ES9218_IFACE_FORMAT_RJUST = 2, | ||
139 | }; | ||
140 | |||
141 | enum es9218_iface_bits { | ||
142 | ES9218_IFACE_BITS_16 = 0, | ||
143 | ES9218_IFACE_BITS_24 = 1, | ||
144 | ES9218_IFACE_BITS_32 = 2, | ||
145 | }; | ||
146 | |||
147 | enum es9218_filter_type { | ||
148 | ES9218_FILTER_LINEAR_FAST = 0, | ||
149 | ES9218_FILTER_LINEAR_SLOW = 1, | ||
150 | ES9218_FILTER_MINIMUM_FAST = 2, | ||
151 | ES9218_FILTER_MINIMUM_SLOW = 3, | ||
152 | ES9218_FILTER_APODIZING_1 = 4, | ||
153 | ES9218_FILTER_APODIZING_2 = 5, | ||
154 | ES9218_FILTER_HYBRID_FAST = 6, | ||
155 | ES9218_FILTER_BRICK_WALL = 7, | ||
156 | }; | ||
157 | |||
158 | /* Power DAC on or off */ | ||
159 | extern void es9218_open(void); | ||
160 | extern void es9218_close(void); | ||
161 | |||
162 | /* Clock controls | ||
163 | * | ||
164 | * - Clock gear divides the input master clock to produce the DAC's clock. | ||
165 | * Frequency can be lowered to save power when using lower sample rates. | ||
166 | * | ||
167 | * - NCO (numerically controller oscillator), according to the datasheet, | ||
168 | * defines the ratio between the DAC's clock and the FSR (for PCM modes, | ||
169 | * this is I2S frame clock = sample rate). In master mode it effectively | ||
170 | * controls the sampling frequency by setting the I2S frame clock output. | ||
171 | * It can also be used in slave mode, but other parts of the datasheet | ||
172 | * say contradictory things about synchronous operation in slave mode. | ||
173 | * | ||
174 | * - If using NCO mode and a varying MCLK input (eg. input from the SoC) then | ||
175 | * you will need to call es9218_recompute_nco() when changing MCLK in order | ||
176 | * to refresh the NCO setting. | ||
177 | */ | ||
178 | extern void es9218_set_clock_gear(enum es9218_clock_gear gear); | ||
179 | extern void es9218_set_nco_frequency(uint32_t fsr); | ||
180 | extern void es9218_recompute_nco(void); | ||
181 | |||
182 | /* Amplifier controls */ | ||
183 | extern void es9218_set_amp_mode(enum es9218_amp_mode mode); | ||
184 | extern void es9218_set_amp_powered(bool en); | ||
185 | |||
186 | /* Interface selection */ | ||
187 | extern void es9218_set_iface_role(enum es9218_iface_role role); | ||
188 | extern void es9218_set_iface_format(enum es9218_iface_format fmt, | ||
189 | enum es9218_iface_bits bits); | ||
190 | |||
191 | /* Volume controls, all volumes given in units of dB/10 */ | ||
192 | extern void es9218_set_dig_volume(int vol_l, int vol_r); | ||
193 | extern void es9218_set_amp_volume(int vol); | ||
194 | |||
195 | /* System mute */ | ||
196 | extern void es9218_mute(bool muted); | ||
197 | |||
198 | /* Oversampling filter */ | ||
199 | extern void es9218_set_filter(enum es9218_filter_type filt); | ||
200 | |||
201 | /* Automute settings */ | ||
202 | extern void es9218_set_automute_time(int time); | ||
203 | extern void es9218_set_automute_level(int dB); | ||
204 | extern void es9218_set_automute_fast_mode(bool en); | ||
205 | |||
206 | /* DPLL bandwidth setting (knob = 0-15) */ | ||
207 | extern void es9218_set_dpll_bandwidth(int knob); | ||
208 | |||
209 | /* THD compensation */ | ||
210 | extern void es9218_set_thd_compensation(bool en); | ||
211 | extern void es9218_set_thd_coeffs(uint16_t c2, uint16_t c3); | ||
212 | |||
213 | /* Direct register read/write/update operations */ | ||
214 | extern int es9218_read(int reg); | ||
215 | extern void es9218_write(int reg, uint8_t val); | ||
216 | extern void es9218_update(int reg, uint8_t msk, uint8_t val); | ||
217 | |||
218 | /* GPIO pin setting callbacks */ | ||
219 | extern void es9218_set_power_pin(int level); | ||
220 | extern void es9218_set_reset_pin(int level); | ||
221 | |||
222 | /* XI(MCLK) getter -- supplied by the target. | ||
223 | * | ||
224 | * Note: when changing the supplied MCLK frequency, the NCO will need to be | ||
225 | * reprogrammed for the new master clock. Call es9218_recompute_nco() to | ||
226 | * force this. Not necessary if you're not using NCO mode. | ||
227 | */ | ||
228 | extern uint32_t es9218_get_mclk(void); | ||
229 | |||
230 | #endif /* __ES9218_H__ */ | ||