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author | Tomasz Moń <desowin@gmail.com> | 2021-06-14 21:15:04 +0200 |
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committer | Tomasz Moń <desowin@gmail.com> | 2021-06-15 07:31:29 +0000 |
commit | f6c7407cc3304f569ff58d4719e431a9f65e3840 (patch) | |
tree | 5b0987c4869fe4c14a4358c1ad7d65efb7fe2fb4 /firmware/export/dm320.h | |
parent | 95408f2117fdcac26662a2f020664d39c774e2c9 (diff) | |
download | rockbox-f6c7407cc3304f569ff58d4719e431a9f65e3840.tar.gz rockbox-f6c7407cc3304f569ff58d4719e431a9f65e3840.zip |
DM320: Use SD/MMC data done interrupt
Wait on semaphore until DMA finishes instead of busy waiting. This
allows the CPU to be used by other tasks during transfers.
Increase peripheral clock frequency, divide AHB by 2 instead of 3.
Function clock frequency is AHB divided by MMC divider + 1.
Change-Id: Ic890634da7e3541962ea3501eae8fa2ca2db606a
Diffstat (limited to 'firmware/export/dm320.h')
-rw-r--r-- | firmware/export/dm320.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index def8508b0b..01f206bfc9 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -930,11 +930,27 @@ extern unsigned long _ttbstart; | |||
930 | #define MMC_ST1_DXFULL (1 << 3) | 930 | #define MMC_ST1_DXFULL (1 << 3) |
931 | #define MMC_ST1_DAT3ST (1 << 4) | 931 | #define MMC_ST1_DAT3ST (1 << 4) |
932 | 932 | ||
933 | #define MMC_IE_EDATDNE (1 << 0) | ||
934 | #define MMC_IE_EBSYDNE (1 << 1) | ||
935 | #define MMC_IE_ERSPDNE (1 << 2) | ||
936 | #define MMC_IE_ETOUTRD (1 << 3) | ||
937 | #define MMC_IE_ETOUTRS (1 << 4) | ||
938 | #define MMC_IE_ECRCWR (1 << 5) | ||
939 | #define MMC_IE_ECRCRD (1 << 6) | ||
940 | #define MMC_IE_ECRCRS (1 << 7) | ||
941 | #define MMC_IE_EDXRDY (1 << 9) | ||
942 | #define MMC_IE_EDRRDY (1 << 10) | ||
943 | #define MMC_IE_EDATED (1 << 11) | ||
944 | |||
933 | #define MMC_DMAMODE_RD_WORDSWAP (1 << 10) | 945 | #define MMC_DMAMODE_RD_WORDSWAP (1 << 10) |
934 | #define MMC_DMAMODE_WR_WORDSWAP (1 << 11) | 946 | #define MMC_DMAMODE_WR_WORDSWAP (1 << 11) |
935 | #define MMC_DMAMODE_WRITE (1 << 12) | 947 | #define MMC_DMAMODE_WRITE (1 << 12) |
936 | #define MMC_DMAMODE_ENABLE (1 << 13) | 948 | #define MMC_DMAMODE_ENABLE (1 << 13) |
937 | #define MMC_DMAMODE_TIMEOUTIRQ_EN (1 << 14) | 949 | #define MMC_DMAMODE_TIMEOUTIRQ_EN (1 << 14) |
950 | |||
951 | #define MMC_DMASTAT1_RUNST (1 << 12) | ||
952 | #define MMC_DMASTAT1_TOUTDT (1 << 13) | ||
953 | |||
938 | /* | 954 | /* |
939 | * IO_EINTx bits | 955 | * IO_EINTx bits |
940 | */ | 956 | */ |
@@ -1001,6 +1017,7 @@ extern unsigned long _ttbstart; | |||
1001 | #define INTR_IRQ1_EXT0 INTR_EINT1_EXT0 | 1017 | #define INTR_IRQ1_EXT0 INTR_EINT1_EXT0 |
1002 | #define INTR_IRQ1_EXT2 INTR_EINT1_EXT2 | 1018 | #define INTR_IRQ1_EXT2 INTR_EINT1_EXT2 |
1003 | #define INTR_IRQ1_EXT7 INTR_EINT1_EXT7 | 1019 | #define INTR_IRQ1_EXT7 INTR_EINT1_EXT7 |
1020 | #define INTR_IRQ1_MMCSDMS0 INTR_EINT1_MMCSDMS0 | ||
1004 | #define INTR_IRQ1_MTC0 INTR_EINT1_MTC0 | 1021 | #define INTR_IRQ1_MTC0 INTR_EINT1_MTC0 |
1005 | 1022 | ||
1006 | /* | 1023 | /* |