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authorAndy <andy@rockbox.org>2005-06-16 00:04:47 +0000
committerAndy <andy@rockbox.org>2005-06-16 00:04:47 +0000
commit3de5e74abad0f7a0782a16a3d7b41e6f07c475d5 (patch)
treea6b3710ab472e38a22aa96576063bbdf2e4d35a5 /firmware/drivers
parenteadceed6f46e5e7e4beedb26a6859d9a9081c3a6 (diff)
downloadrockbox-3de5e74abad0f7a0782a16a3d7b41e6f07c475d5.tar.gz
rockbox-3de5e74abad0f7a0782a16a3d7b41e6f07c475d5.zip
uda1380: Added bass/treble and recording functions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6729 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers')
-rw-r--r--firmware/drivers/uda1380.c127
1 files changed, 111 insertions, 16 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c
index 4b63ccd744..4eb04d1ba3 100644
--- a/firmware/drivers/uda1380.c
+++ b/firmware/drivers/uda1380.c
@@ -39,27 +39,28 @@
39int uda1380_write_reg(unsigned char reg, unsigned short value); 39int uda1380_write_reg(unsigned char reg, unsigned short value);
40unsigned short uda1380_regs[0x30]; 40unsigned short uda1380_regs[0x30];
41 41
42/* Definition of a good (?) configuration to start with */ 42/* Definition of a playback configuration to start with */
43/* Not enabling ADC for now.. */
44 43
45#define NUM_DEFAULT_REGS 13 44#define NUM_DEFAULT_REGS 13
46unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] = 45unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
47{ 46{
48 REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50, 47 REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50,
49 REG_I2S, I2S_IFMT_IIS, 48 REG_I2S, I2S_IFMT_IIS,
50 REG_PWR, PON_PLL | PON_DAC | PON_BIAS, /* PON_HP is enabled later */ 49 REG_PWR, PON_PLL | PON_DAC | PON_BIAS, /* PON_HP is enabled later */
51 REG_AMIX, AMIX_RIGHT(0x10) | AMIX_LEFT(0x10), /* 00=max, 3f=mute */ 50 REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f), /* 00=max, 3f=mute */
52 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */ 51 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */
53 REG_MIX_VOL, MIX_VOL_CHANNEL_1(0) | MIX_VOL_CHANNEL_2(0xff), /* 00=max, ff=mute */ 52 REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff), /* 00=max, ff=mute */
54 REG_EQ, 0, 53 REG_EQ, EQ_MODE_MAX, /* Bass and tremble = 0 dB */
55 REG_MUTE, MUTE_MASTER, /* Mute everything to start with */ 54 REG_MUTE, MUTE_MASTER, /* Mute everything to start with */
56 REG_MIX_CTL, 0, 55 REG_MIX_CTL, 0,
57 REG_DEC_VOL, 0, 56 REG_DEC_VOL, 0,
58 REG_PGA, MUTE_ADC, 57 REG_PGA, MUTE_ADC,
59 REG_ADC, SKIP_DCFIL, 58 REG_ADC, SKIP_DCFIL,
60 REG_AGC, 0 59 REG_AGC, 0
61}; 60};
62 61
62
63
63/* Returns 0 if register was written or -1 if write failed */ 64/* Returns 0 if register was written or -1 if write failed */
64int uda1380_write_reg(unsigned char reg, unsigned short value) 65int uda1380_write_reg(unsigned char reg, unsigned short value)
65{ 66{
@@ -93,6 +94,22 @@ int uda1380_setvol(int vol)
93 MASTER_VOL_LEFT(vol) | MASTER_VOL_RIGHT(vol)); 94 MASTER_VOL_LEFT(vol) | MASTER_VOL_RIGHT(vol));
94} 95}
95 96
97/**
98 * Sets the bass value (0-15)
99 */
100void uda1380_set_bass(int value)
101{
102 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK) | BASSL(value) | BASSR(value));
103}
104
105/**
106 * Sets the treble value (0-3)
107 */
108void uda1380_set_treble(int value)
109{
110 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK) | TREBLEL(value) | TREBLER(value));
111}
112
96/** 113/**
97 * Mute (mute=1) or enable sound (mute=0) 114 * Mute (mute=1) or enable sound (mute=0)
98 * 115 *
@@ -163,3 +180,81 @@ void uda1380_close(void)
163 uda1380_write_reg(REG_PWR, 0); 180 uda1380_write_reg(REG_PWR, 0);
164 uda1380_write_reg(REG_0, 0); /* Disable codec */ 181 uda1380_write_reg(REG_0, 0); /* Disable codec */
165} 182}
183
184/**
185 * Calling this function enables the UDA1380 to send
186 * sound samples over the I2S bus, which is connected
187 * to the processor's IIS1 interface.
188 *
189 * source_mic: true=record from microphone, false=record from line-in
190 */
191void uda1380_enable_recording(bool source_mic)
192{
193 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
194
195 if (source_mic)
196 {
197 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
198 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) | SEL_LNA | SEL_MIC | EN_DCFIL); /* VGA_GAIN: 0=0 dB, F=30dB */
199 uda1380_write_reg(REG_PGA, 0);
200 } else
201 {
202 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL | PON_PGAR | PON_ADCR);
203 uda1380_write_reg(REG_ADC, EN_DCFIL);
204 uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & PGA_GAIN_MASK) | PGA_GAINL(0) | PGA_GAINR(0)); /* PGA_GAIN: 0=0 dB, F=24dB */
205 }
206
207 uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
208 uda1380_write_reg(REG_MIX_CTL, MIX_MODE(3)); /* Not sure which mode is the best one.. */
209
210}
211
212/**
213 * Stop sending samples on the I2S bus
214 */
215void uda1380_disable_recording(void)
216{
217 uda1380_write_reg(REG_PGA, MUTE_ADC);
218 sleep(HZ/8);
219
220 uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
221 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~(PON_LNA | PON_ADCL | PON_ADCR | PON_PGAL | PON_PGAR));
222 uda1380_write_reg(REG_0, uda1380_regs[REG_0] & ~EN_ADC);
223 uda1380_write_reg(REG_ADC, SKIP_DCFIL);
224}
225
226/**
227 * Set recording gain and volume
228 *
229 * mic_gain : range 0 .. 15 -> 0 .. 30 dB gain
230 * linein_gain : range 0 .. 15 -> 0 .. 24 dB gain
231 *
232 * adc_volume : range -127 .. 48 -> -63 .. 24 dB gain
233 * note that 0 -> 0 dB gain..
234 */
235void uda1380_set_recvol(int mic_gain, int linein_gain, int adc_volume)
236{
237 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(adc_volume) | DEC_VOLR(adc_volume));
238 uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK) | PGA_GAINL(linein_gain) | PGA_GAINR(linein_gain));
239 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & ~VGA_GAIN_MASK) | VGA_GAIN(mic_gain));
240}
241
242
243/**
244 * Enable or disable recording monitor (so one can listen to the recording)
245 *
246 */
247void uda1380_set_monitor(int enable)
248{
249 if (enable)
250 {
251 /* enable channel 2 */
252 uda1380_write_reg(REG_MIX_VOL, (uda1380_regs[REG_MIX_VOL] & 0x00FF) | MIX_VOL_CH_2(0));
253 uda1380_write_reg(REG_MUTE, 0);
254 } else
255 {
256 /* mute channel 2 */
257 uda1380_write_reg(REG_MUTE, MUTE_CH2);
258 uda1380_write_reg(REG_MIX_VOL, (uda1380_regs[REG_MIX_VOL] & 0x00FF) | MIX_VOL_CH_2(0xff));
259 }
260}