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authorMiika Pekkarinen <miipekk@ihme.org>2005-07-03 15:25:06 +0000
committerMiika Pekkarinen <miipekk@ihme.org>2005-07-03 15:25:06 +0000
commit349f39a7f4a0b78dc1e6e9e6bcbe6f484471cb74 (patch)
tree773b4b1270d9b7d34165db55156ef283e88ef377 /firmware/drivers
parentbb3ed3cda98dc59719f5ab48fafc542eaa0d29a0 (diff)
downloadrockbox-349f39a7f4a0b78dc1e6e9e6bcbe6f484471cb74.tar.gz
rockbox-349f39a7f4a0b78dc1e6e9e6bcbe6f484471cb74.zip
Fixed pops when starting playback.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6993 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers')
-rw-r--r--firmware/drivers/uda1380.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c
index 07e92e7bba..1636f13365 100644
--- a/firmware/drivers/uda1380.c
+++ b/firmware/drivers/uda1380.c
@@ -53,7 +53,7 @@ unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
53 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */ 53 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */
54 REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff), /* 00=max, ff=mute */ 54 REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff), /* 00=max, ff=mute */
55 REG_EQ, EQ_MODE_MAX, /* Bass and tremble = 0 dB */ 55 REG_EQ, EQ_MODE_MAX, /* Bass and tremble = 0 dB */
56 REG_MUTE, MUTE_MASTER, /* Mute everything to start with */ 56 REG_MUTE, MUTE_MASTER | MUTE_CH2, /* Mute everything to start with */
57 REG_MIX_CTL, MIX_CTL_MIX, /* Enable mixer */ 57 REG_MIX_CTL, MIX_CTL_MIX, /* Enable mixer */
58 REG_DEC_VOL, 0, 58 REG_DEC_VOL, 0,
59 REG_PGA, MUTE_ADC, 59 REG_PGA, MUTE_ADC,
@@ -158,8 +158,6 @@ void uda1380_enable_output(bool enable)
158{ 158{
159 if (enable) { 159 if (enable) {
160 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_HP); 160 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_HP);
161 /* Don't unmute audio output here */
162 // uda1380_write_reg(REG_MUTE, MUTE_CH2);
163 } else { 161 } else {
164 uda1380_write_reg(REG_MUTE, MUTE_MASTER); 162 uda1380_write_reg(REG_MUTE, MUTE_MASTER);
165 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~PON_HP); 163 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~PON_HP);