diff options
author | Bob Cousins <bobc@rockbox.org> | 2009-11-01 22:58:08 +0000 |
---|---|---|
committer | Bob Cousins <bobc@rockbox.org> | 2009-11-01 22:58:08 +0000 |
commit | 33040275cfccdc1f1c33e0a9ef3b5a2b88aa3679 (patch) | |
tree | b985669b775e9f482ca1d724f09d8a5cc74cd1cb /firmware/drivers/audio | |
parent | 5d40b9a24a5ffe096691fbc117c718561d4bb30c (diff) | |
download | rockbox-33040275cfccdc1f1c33e0a9ef3b5a2b88aa3679.tar.gz rockbox-33040275cfccdc1f1c33e0a9ef3b5a2b88aa3679.zip |
Improvements to mini2440/UDA1341 audio
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23478 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers/audio')
-rw-r--r-- | firmware/drivers/audio/uda1341.c | 76 |
1 files changed, 69 insertions, 7 deletions
diff --git a/firmware/drivers/audio/uda1341.c b/firmware/drivers/audio/uda1341.c index f9d95eff02..0171169942 100644 --- a/firmware/drivers/audio/uda1341.c +++ b/firmware/drivers/audio/uda1341.c | |||
@@ -33,9 +33,9 @@ const struct sound_settings_info audiohw_settings[] = { | |||
33 | [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25}, | 33 | [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25}, |
34 | [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0}, | 34 | [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0}, |
35 | [SOUND_TREBLE] = {"dB", 0, 2, 0, 6, 0}, | 35 | [SOUND_TREBLE] = {"dB", 0, 2, 0, 6, 0}, |
36 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, | 36 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, /* not used */ |
37 | [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0}, | 37 | [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0}, /* not used */ |
38 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, | 38 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, /* not used */ |
39 | #ifdef HAVE_RECORDING | 39 | #ifdef HAVE_RECORDING |
40 | [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0}, | 40 | [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0}, |
41 | [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0}, | 41 | [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0}, |
@@ -43,6 +43,17 @@ const struct sound_settings_info audiohw_settings[] = { | |||
43 | #endif | 43 | #endif |
44 | }; | 44 | }; |
45 | 45 | ||
46 | /* convert tenth of dB volume (-600..0) to master volume register value */ | ||
47 | int tenthdb2master(int db) | ||
48 | { | ||
49 | if (db < -600) | ||
50 | return 63; | ||
51 | else /* 1 dB steps */ | ||
52 | return -(db / 10) + 1; | ||
53 | } | ||
54 | |||
55 | static unsigned short uda_regs[NUM_REG_ID]; | ||
56 | |||
46 | /****************************************************************************/ | 57 | /****************************************************************************/ |
47 | 58 | ||
48 | /* ------------------------------------------------- */ | 59 | /* ------------------------------------------------- */ |
@@ -59,7 +70,7 @@ const struct sound_settings_info audiohw_settings[] = { | |||
59 | static void l3_init (void) | 70 | static void l3_init (void) |
60 | { | 71 | { |
61 | L3PORT |= L3MODE | L3CLOCK; | 72 | L3PORT |= L3MODE | L3CLOCK; |
62 | L3PORT &= L3DATA; | 73 | L3PORT &= ~L3DATA; |
63 | 74 | ||
64 | S3C2440_GPIO_CONFIG (GPBCON, 2, GPIO_OUTPUT); /* L3 MODE */ | 75 | S3C2440_GPIO_CONFIG (GPBCON, 2, GPIO_OUTPUT); /* L3 MODE */ |
65 | S3C2440_GPIO_CONFIG (GPBCON, 3, GPIO_OUTPUT); /* L3 DATA */ | 76 | S3C2440_GPIO_CONFIG (GPBCON, 3, GPIO_OUTPUT); /* L3 DATA */ |
@@ -72,8 +83,8 @@ static void l3_init (void) | |||
72 | 83 | ||
73 | static void bit_delay (void) | 84 | static void bit_delay (void) |
74 | { | 85 | { |
75 | int j; | 86 | volatile int j; |
76 | for (j=0; j<4; j++) | 87 | for (j=0; j<5; j++) |
77 | ; | 88 | ; |
78 | } | 89 | } |
79 | 90 | ||
@@ -86,6 +97,7 @@ static void l3_write_byte (unsigned char data, bool address_mode) | |||
86 | L3PORT &= ~L3MODE; | 97 | L3PORT &= ~L3MODE; |
87 | else | 98 | else |
88 | L3PORT |= L3MODE; | 99 | L3PORT |= L3MODE; |
100 | bit_delay(); | ||
89 | 101 | ||
90 | for (bit=0; bit < 8; bit++) | 102 | for (bit=0; bit < 8; bit++) |
91 | { | 103 | { |
@@ -144,41 +156,91 @@ static void udacodec_reset(void) | |||
144 | I2S_IFMT_IIS); | 156 | I2S_IFMT_IIS); |
145 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_0 | UDA_SYSCLK_256FS | I2S_IFMT_IIS); | 157 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_0 | UDA_SYSCLK_256FS | I2S_IFMT_IIS); |
146 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_1 | UDA_POWER_DAC_ON); | 158 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_1 | UDA_POWER_DAC_ON); |
159 | |||
160 | uda_regs[UDA_REG_ID_CTRL2] = UDA_PEAK_DETECT_POS_AFTER | | ||
161 | UDA_DE_EMPHASIS_NONE | UDA_MUTE_OFF | UDA_MODE_SWITCH_FLAT; | ||
162 | |||
147 | } | 163 | } |
148 | 164 | ||
149 | /****************************************************************************/ | 165 | /****************************************************************************/ |
150 | 166 | ||
151 | /* Audio API functions */ | 167 | /* Audio API functions */ |
152 | 168 | ||
169 | /* This table must match the table in pcm-xxxx.c if using Master mode */ | ||
170 | /* [reserved, master clock rate] */ | ||
171 | static const unsigned char uda_freq_parms[HW_NUM_FREQ][2] = | ||
172 | { | ||
173 | [HW_FREQ_64] = { 0, UDA_SYSCLK_256FS }, | ||
174 | [HW_FREQ_44] = { 0, UDA_SYSCLK_384FS }, | ||
175 | [HW_FREQ_22] = { 0, UDA_SYSCLK_256FS }, | ||
176 | [HW_FREQ_11] = { 0, UDA_SYSCLK_256FS }, | ||
177 | }; | ||
178 | |||
153 | void audiohw_init(void) | 179 | void audiohw_init(void) |
154 | { | 180 | { |
155 | udacodec_reset(); | 181 | udacodec_reset(); |
182 | |||
183 | audiohw_set_bass (0); | ||
184 | audiohw_set_treble (0); | ||
185 | audiohw_set_master_vol (26, 26); /* -25 dB */ | ||
156 | } | 186 | } |
157 | 187 | ||
188 | void audiohw_postinit(void) | ||
189 | { | ||
190 | } | ||
191 | |||
158 | void audiohw_close(void) | 192 | void audiohw_close(void) |
159 | { | 193 | { |
194 | /* DAC, ADC off */ | ||
195 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_1 | 0); | ||
160 | } | 196 | } |
161 | 197 | ||
162 | void audiohw_set_bass(int value) | 198 | void audiohw_set_bass(int value) |
163 | { | 199 | { |
200 | uda_regs [UDA_REG_ID_CTRL1] &= UDA_BASS_BOOST (UDA_BASS_BOOST_MASK); | ||
201 | uda_regs [UDA_REG_ID_CTRL1] |= UDA_BASS_BOOST (value & UDA_BASS_BOOST_MASK); | ||
202 | |||
203 | udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL1 | uda_regs [UDA_REG_ID_CTRL1] ); | ||
164 | } | 204 | } |
165 | 205 | ||
166 | void audiohw_set_treble(int value) | 206 | void audiohw_set_treble(int value) |
167 | { | 207 | { |
208 | uda_regs [UDA_REG_ID_CTRL1] &= UDA_TREBLE (UDA_TREBLE_MASK); | ||
209 | uda_regs [UDA_REG_ID_CTRL1] |= UDA_TREBLE (value & UDA_TREBLE_MASK); | ||
210 | |||
211 | udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL1 | uda_regs [UDA_REG_ID_CTRL1] ); | ||
168 | } | 212 | } |
169 | 213 | ||
170 | void audiohw_mute(bool mute) | 214 | void audiohw_mute(bool mute) |
171 | { | 215 | { |
216 | if (mute) | ||
217 | uda_regs [UDA_REG_ID_CTRL2] |= UDA_MUTE_ON; | ||
218 | else | ||
219 | uda_regs [UDA_REG_ID_CTRL2] &= ~UDA_MUTE_ON; | ||
220 | |||
221 | udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL2 | uda_regs [UDA_REG_ID_CTRL2] ); | ||
172 | } | 222 | } |
173 | 223 | ||
174 | void audiohw_set_prescaler(int val) | 224 | void audiohw_set_prescaler(int val) |
175 | { | 225 | { |
226 | (void)val; | ||
176 | } | 227 | } |
177 | 228 | ||
178 | void audiohw_postinit(void) | 229 | /** |
230 | * Sets left and right master volume (1(max) to 62(muted)) | ||
231 | */ | ||
232 | void audiohw_set_master_vol(int vol_l, int vol_r) | ||
179 | { | 233 | { |
234 | uda_regs[UDA_REG_ID_CTRL0] = (vol_l + vol_r) / 2; | ||
235 | udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL0 | uda_regs[UDA_REG_ID_CTRL0]); | ||
180 | } | 236 | } |
181 | 237 | ||
182 | void audiohw_set_frequency(int fsel) | 238 | void audiohw_set_frequency(int fsel) |
183 | { | 239 | { |
240 | if ((unsigned)fsel >= HW_NUM_FREQ) | ||
241 | fsel = HW_FREQ_DEFAULT; | ||
242 | |||
243 | uda_regs[UDA_REG_ID_STATUS_0] = I2S_IFMT_IIS | uda_freq_parms[fsel][1]; | ||
244 | |||
245 | udacodec_write (UDA_REG_STATUS, UDA_STATUS_0 | uda_regs[UDA_REG_ID_STATUS_0]); | ||
184 | } | 246 | } |