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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-01-11 13:58:03 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-01-16 19:17:25 -0500 |
commit | 18b3e91707e42873eab833f0f3da709062207ba7 (patch) | |
tree | 7a5ebfc65961713243b607e83fba9e3758cbcc45 /firmware/drivers/audio/x1000-codec.c | |
parent | 15e3d37110f1674ec7d52c2f055ebfad1d77b5da (diff) | |
download | rockbox-18b3e91707e42873eab833f0f3da709062207ba7.tar.gz rockbox-18b3e91707e42873eab833f0f3da709062207ba7.zip |
x1000: internal codec audio driver
Change-Id: I2eb551ec6b593951c33ae6b93df2a23dc6612c43
Diffstat (limited to 'firmware/drivers/audio/x1000-codec.c')
-rw-r--r-- | firmware/drivers/audio/x1000-codec.c | 286 |
1 files changed, 286 insertions, 0 deletions
diff --git a/firmware/drivers/audio/x1000-codec.c b/firmware/drivers/audio/x1000-codec.c new file mode 100644 index 0000000000..c083882dab --- /dev/null +++ b/firmware/drivers/audio/x1000-codec.c | |||
@@ -0,0 +1,286 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021-2022 Aidan MacDonald | ||
11 | * Copyright 2014 Ingenic Semiconductor Co.,Ltd | ||
12 | * cscheng <shicheng.cheng@ingenic.com> | ||
13 | * sound/soc/ingenic/icodec/icdc_d3.c | ||
14 | * ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or | ||
17 | * modify it under the terms of the GNU General Public License | ||
18 | * as published by the Free Software Foundation; either version 2 | ||
19 | * of the License, or (at your option) any later version. | ||
20 | * | ||
21 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
22 | * KIND, either express or implied. | ||
23 | * | ||
24 | ****************************************************************************/ | ||
25 | |||
26 | #include "x1000-codec.h" | ||
27 | #include "audiohw.h" | ||
28 | #include "pcm_sampr.h" | ||
29 | #include "kernel.h" | ||
30 | #include "x1000/aic.h" | ||
31 | |||
32 | static const uint8_t fsel_to_hw[HW_NUM_FREQ] = { | ||
33 | [0 ... HW_NUM_FREQ-1] = 0, | ||
34 | HW_HAVE_8_([HW_FREQ_8] = 0,) | ||
35 | HW_HAVE_11_([HW_FREQ_11] = 1,) | ||
36 | HW_HAVE_12_([HW_FREQ_12] = 2,) | ||
37 | HW_HAVE_16_([HW_FREQ_16] = 3,) | ||
38 | HW_HAVE_22_([HW_FREQ_22] = 4,) | ||
39 | HW_HAVE_24_([HW_FREQ_24] = 5,) | ||
40 | HW_HAVE_32_([HW_FREQ_32] = 6,) | ||
41 | HW_HAVE_44_([HW_FREQ_44] = 7,) | ||
42 | HW_HAVE_48_([HW_FREQ_48] = 8,) | ||
43 | HW_HAVE_88_([HW_FREQ_88] = 9,) | ||
44 | HW_HAVE_96_([HW_FREQ_96] = 10,) | ||
45 | HW_HAVE_176_([HW_FREQ_176] = 11,) | ||
46 | HW_HAVE_192_([HW_FREQ_192] = 12,) | ||
47 | }; | ||
48 | |||
49 | void x1000_icodec_open(void) | ||
50 | { | ||
51 | /* Ingenic does not specify any timing constraints for reset, | ||
52 | * let's do a 1ms delay for fun */ | ||
53 | jz_writef(AIC_RGADW, ICRST(1)); | ||
54 | mdelay(1); | ||
55 | jz_writef(AIC_RGADW, ICRST(0)); | ||
56 | |||
57 | /* Power-up and initial config sequence */ | ||
58 | static const uint8_t init_config[] = { | ||
59 | JZCODEC_CR_VIC, 0x03, /* ensure codec is powered off */ | ||
60 | JZCODEC_CR_CK, 0x40, /* MCLK_DIV=1, SHUTDOWN_CLK=0, CRYSTAL=12Mhz */ | ||
61 | JZCODEC_AICR_DAC, 0x13, /* ADWL=0 (16bit word length) | ||
62 | * SLAVE=0 (i2s master mode) | ||
63 | * SB_DAC=1 (power down DAC) | ||
64 | * AUDIOIF=3 (i2s mode) */ | ||
65 | JZCODEC_AICR_ADC, 0x13, /* ADWL=0 (16bit word length) | ||
66 | * SB_ADC=1 (power down ADC) | ||
67 | * AUDIOIF=3 (i2s mode) | ||
68 | */ | ||
69 | JZCODEC_CR_DAC, 0x91, /* DAC mute, power down */ | ||
70 | JZCODEC_CR_DAC2, 0x38, /* DAC power down */ | ||
71 | JZCODEC_CR_DMIC, 0x00, /* DMIC clock off */ | ||
72 | JZCODEC_CR_MIC1, 0x30, /* MIC1 power down */ | ||
73 | JZCODEC_CR_MIC2, 0x30, /* MIC2 power down */ | ||
74 | JZCODEC_CR_ADC, 0x90, /* ADC mute, power down */ | ||
75 | JZCODEC_ICR, 0x00, /* INT_FORM=0 (high level IRQ) */ | ||
76 | JZCODEC_IMR, 0xff, /* Mask all interrupts */ | ||
77 | JZCODEC_IMR2, 0xff, | ||
78 | JZCODEC_IFR, 0xff, /* Clear all interrupt flags */ | ||
79 | JZCODEC_IFR2, 0xff, | ||
80 | }; | ||
81 | |||
82 | for(size_t i = 0; i < ARRAYLEN(init_config); i += 2) | ||
83 | x1000_icodec_write(init_config[i], init_config[i+1]); | ||
84 | |||
85 | /* SB -> 0 (power up) */ | ||
86 | x1000_icodec_write(JZCODEC_CR_VIC, 0x02); | ||
87 | mdelay(250); | ||
88 | |||
89 | /* Initial gain setting. Apparently we need to set one gain and | ||
90 | * then set another after 10ms; afterward it can be changed freely. */ | ||
91 | static const uint8_t gain_regs[] = { | ||
92 | JZCODEC_GCR_DACL, | ||
93 | JZCODEC_GCR_DACR, | ||
94 | JZCODEC_GCR_DACL2, | ||
95 | JZCODEC_GCR_DACR2, | ||
96 | JZCODEC_GCR_MIC1, | ||
97 | JZCODEC_GCR_MIC2, | ||
98 | JZCODEC_GCR_ADCL, | ||
99 | JZCODEC_GCR_ADCR, | ||
100 | }; | ||
101 | |||
102 | for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i) | ||
103 | x1000_icodec_write(gain_regs[i], 0); | ||
104 | |||
105 | mdelay(10); | ||
106 | |||
107 | for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i) | ||
108 | x1000_icodec_write(gain_regs[i], 1); | ||
109 | |||
110 | /* SB_SLEEP -> 0 (exit sleep/standby mode) */ | ||
111 | x1000_icodec_write(JZCODEC_CR_VIC, 0x00); | ||
112 | mdelay(200); | ||
113 | } | ||
114 | |||
115 | void x1000_icodec_close(void) | ||
116 | { | ||
117 | /* SB_SLEEP -> 1 (enable sleep mode) */ | ||
118 | x1000_icodec_write(JZCODEC_CR_VIC, 0x02); | ||
119 | |||
120 | /* SB -> 1 (power down) */ | ||
121 | x1000_icodec_write(JZCODEC_CR_VIC, 0x03); | ||
122 | } | ||
123 | |||
124 | /* | ||
125 | * DAC configuration | ||
126 | */ | ||
127 | |||
128 | void x1000_icodec_dac_frequency(int fsel) | ||
129 | { | ||
130 | x1000_icodec_update(JZCODEC_FCR_DAC, 0x0f, fsel_to_hw[fsel]); | ||
131 | } | ||
132 | |||
133 | /* | ||
134 | * ADC configuration | ||
135 | */ | ||
136 | |||
137 | void x1000_icodec_adc_enable(bool en) | ||
138 | { | ||
139 | x1000_icodec_update(JZCODEC_AICR_ADC, 0x10, en ? 0x00 : 0x10); | ||
140 | x1000_icodec_update(JZCODEC_CR_ADC, 0x10, en ? 0x00 : 0x10); | ||
141 | } | ||
142 | |||
143 | void x1000_icodec_adc_mute(bool muted) | ||
144 | { | ||
145 | x1000_icodec_update(JZCODEC_CR_ADC, 0x80, muted ? 0x80 : 0x00); | ||
146 | } | ||
147 | |||
148 | void x1000_icodec_adc_mic_sel(int sel) | ||
149 | { | ||
150 | x1000_icodec_update(JZCODEC_CR_ADC, 0x40, | ||
151 | sel == JZCODEC_MIC_SEL_DIGITAL ? 0x40 : 0x00); | ||
152 | } | ||
153 | |||
154 | void x1000_icodec_adc_frequency(int fsel) | ||
155 | { | ||
156 | x1000_icodec_update(JZCODEC_FCR_ADC, 0x0f, fsel_to_hw[fsel]); | ||
157 | } | ||
158 | |||
159 | void x1000_icodec_adc_highpass_filter(bool en) | ||
160 | { | ||
161 | x1000_icodec_update(JZCODEC_FCR_ADC, 0x40, en ? 0x40 : 0x00); | ||
162 | } | ||
163 | |||
164 | void x1000_icodec_adc_gain(int gain_dB) | ||
165 | { | ||
166 | if(gain_dB < X1000_ICODEC_ADC_GAIN_MIN) | ||
167 | gain_dB = X1000_ICODEC_ADC_GAIN_MIN; | ||
168 | else if(gain_dB > X1000_ICODEC_ADC_GAIN_MAX) | ||
169 | gain_dB = X1000_ICODEC_ADC_GAIN_MAX; | ||
170 | |||
171 | /* bit 7 = use the same gain for both channels */ | ||
172 | x1000_icodec_write(JZCODEC_GCR_ADCL, 0x80 | gain_dB); | ||
173 | } | ||
174 | |||
175 | /* | ||
176 | * MIC1 configuration | ||
177 | */ | ||
178 | |||
179 | void x1000_icodec_mic1_enable(bool en) | ||
180 | { | ||
181 | x1000_icodec_update(JZCODEC_CR_MIC1, 0x10, en ? 0x00 : 0x10); | ||
182 | } | ||
183 | |||
184 | void x1000_icodec_mic1_bias_enable(bool en) | ||
185 | { | ||
186 | x1000_icodec_update(JZCODEC_CR_MIC1, 0x20, en ? 0x00 : 0x20); | ||
187 | } | ||
188 | |||
189 | void x1000_icodec_mic1_configure(int settings) | ||
190 | { | ||
191 | x1000_icodec_update(JZCODEC_CR_MIC1, JZCODEC_MIC1_CONFIGURE_MASK, | ||
192 | settings & JZCODEC_MIC1_CONFIGURE_MASK); | ||
193 | } | ||
194 | |||
195 | void x1000_icodec_mic1_gain(int gain_dB) | ||
196 | { | ||
197 | if(gain_dB < X1000_ICODEC_MIC_GAIN_MIN) | ||
198 | gain_dB = X1000_ICODEC_MIC_GAIN_MIN; | ||
199 | else if(gain_dB > X1000_ICODEC_MIC_GAIN_MAX) | ||
200 | gain_dB = X1000_ICODEC_MIC_GAIN_MAX; | ||
201 | |||
202 | x1000_icodec_write(JZCODEC_GCR_MIC1, gain_dB/X1000_ICODEC_MIC_GAIN_STEP); | ||
203 | } | ||
204 | |||
205 | /* | ||
206 | * Mixer configuration | ||
207 | */ | ||
208 | |||
209 | void x1000_icodec_mixer_enable(bool en) | ||
210 | { | ||
211 | x1000_icodec_update(JZCODEC_CR_MIX, 0x80, en ? 0x80 : 0x00); | ||
212 | } | ||
213 | |||
214 | /* | ||
215 | * Register access | ||
216 | */ | ||
217 | |||
218 | static int x1000_icodec_read_direct(int reg) | ||
219 | { | ||
220 | jz_writef(AIC_RGADW, ADDR(reg)); | ||
221 | return jz_readf(AIC_RGDATA, DATA); | ||
222 | } | ||
223 | |||
224 | static void x1000_icodec_write_direct(int reg, int value) | ||
225 | { | ||
226 | jz_writef(AIC_RGADW, ADDR(reg), DATA(value)); | ||
227 | jz_writef(AIC_RGADW, RGWR(1)); | ||
228 | while(jz_readf(AIC_RGADW, RGWR)); | ||
229 | } | ||
230 | |||
231 | static void x1000_icodec_update_direct(int reg, int mask, int value) | ||
232 | { | ||
233 | int x = x1000_icodec_read_direct(reg) & ~mask; | ||
234 | x |= value; | ||
235 | x1000_icodec_write_direct(reg, x); | ||
236 | } | ||
237 | |||
238 | static int x1000_icodec_read_indirect(int c_reg, int index) | ||
239 | { | ||
240 | x1000_icodec_update_direct(c_reg, 0x7f, index & 0x3f); | ||
241 | return x1000_icodec_read_direct(c_reg+1); | ||
242 | } | ||
243 | |||
244 | static void x1000_icodec_write_indirect(int c_reg, int index, int value) | ||
245 | { | ||
246 | /* NB: The X1000 programming manual says we should write the data | ||
247 | * register first, but in fact the control register needs to be | ||
248 | * written first (following Ingenic's Linux driver). */ | ||
249 | x1000_icodec_update_direct(c_reg, 0x7f, 0x40 | (index & 0x3f)); | ||
250 | x1000_icodec_write_direct(c_reg+1, value); | ||
251 | } | ||
252 | |||
253 | static void x1000_icodec_update_indirect(int c_reg, int index, int mask, int value) | ||
254 | { | ||
255 | int x = x1000_icodec_read_indirect(c_reg, index) & ~mask; | ||
256 | x |= value; | ||
257 | x1000_icodec_write_indirect(c_reg, index, x); | ||
258 | } | ||
259 | |||
260 | int x1000_icodec_read(int reg) | ||
261 | { | ||
262 | if(reg & JZCODEC_INDIRECT_BIT) | ||
263 | return x1000_icodec_read_indirect(JZCODEC_INDIRECT_CREG(reg), | ||
264 | JZCODEC_INDIRECT_INDEX(reg)); | ||
265 | else | ||
266 | return x1000_icodec_read_direct(reg); | ||
267 | } | ||
268 | |||
269 | void x1000_icodec_write(int reg, int value) | ||
270 | { | ||
271 | if(reg & JZCODEC_INDIRECT_BIT) | ||
272 | return x1000_icodec_write_indirect(JZCODEC_INDIRECT_CREG(reg), | ||
273 | JZCODEC_INDIRECT_INDEX(reg), value); | ||
274 | else | ||
275 | return x1000_icodec_write_direct(reg, value); | ||
276 | } | ||
277 | |||
278 | void x1000_icodec_update(int reg, int mask, int value) | ||
279 | { | ||
280 | if(reg & JZCODEC_INDIRECT_BIT) | ||
281 | return x1000_icodec_update_indirect(JZCODEC_INDIRECT_CREG(reg), | ||
282 | JZCODEC_INDIRECT_INDEX(reg), | ||
283 | mask, value); | ||
284 | else | ||
285 | return x1000_icodec_update_direct(reg, mask, value); | ||
286 | } | ||