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author | Marcoen Hirschberg <marcoen@gmail.com> | 2006-10-30 09:38:34 +0000 |
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committer | Marcoen Hirschberg <marcoen@gmail.com> | 2006-10-30 09:38:34 +0000 |
commit | ede3d646b9a248a1893ec20482eaa30641df078e (patch) | |
tree | d8f851d6d7483e519901b5374b269a0535bc98d9 /firmware/drivers/ata.c | |
parent | 7787cd25f49102ef19db79ea6b9d294653d247c7 (diff) | |
download | rockbox-ede3d646b9a248a1893ec20482eaa30641df078e.tar.gz rockbox-ede3d646b9a248a1893ec20482eaa30641df078e.zip |
move coldfire ata defines to a shared ata-target.h
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11395 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/drivers/ata.c')
-rw-r--r-- | firmware/drivers/ata.c | 46 |
1 files changed, 1 insertions, 45 deletions
diff --git a/firmware/drivers/ata.c b/firmware/drivers/ata.c index 39827f7188..00ef0e8eb5 100644 --- a/firmware/drivers/ata.c +++ b/firmware/drivers/ata.c | |||
@@ -36,51 +36,7 @@ | |||
36 | 36 | ||
37 | #define SECTOR_SIZE (512) | 37 | #define SECTOR_SIZE (512) |
38 | 38 | ||
39 | #if (CONFIG_CPU == MCF5249) || (CONFIG_CPU == MCF5250) | 39 | #if CONFIG_CPU == SH7034 |
40 | |||
41 | /* asm optimised read & write loops */ | ||
42 | |||
43 | #define NOINLINE_ATTR __attribute__((noinline)) /* don't inline the loops */ | ||
44 | |||
45 | #define ATA_IOBASE 0x20000000 | ||
46 | #define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE + 0x20))) | ||
47 | #define ATA_CONTROL (*((volatile unsigned short*)(ATA_IOBASE + 0x1c))) | ||
48 | |||
49 | #define ATA_ERROR (*((volatile unsigned short*)(ATA_IOBASE + 0x22))) | ||
50 | #define ATA_NSECTOR (*((volatile unsigned short*)(ATA_IOBASE + 0x24))) | ||
51 | #define ATA_SECTOR (*((volatile unsigned short*)(ATA_IOBASE + 0x26))) | ||
52 | #define ATA_LCYL (*((volatile unsigned short*)(ATA_IOBASE + 0x28))) | ||
53 | #define ATA_HCYL (*((volatile unsigned short*)(ATA_IOBASE + 0x2a))) | ||
54 | #define ATA_SELECT (*((volatile unsigned short*)(ATA_IOBASE + 0x2c))) | ||
55 | #define ATA_COMMAND (*((volatile unsigned short*)(ATA_IOBASE + 0x2e))) | ||
56 | |||
57 | #define STATUS_BSY 0x8000 | ||
58 | #define STATUS_RDY 0x4000 | ||
59 | #define STATUS_DF 0x2000 | ||
60 | #define STATUS_DRQ 0x0800 | ||
61 | #define STATUS_ERR 0x0100 | ||
62 | |||
63 | #define ERROR_ABRT 0x0400 | ||
64 | |||
65 | #define WRITE_PATTERN1 0xa5 | ||
66 | #define WRITE_PATTERN2 0x5a | ||
67 | #define WRITE_PATTERN3 0xaa | ||
68 | #define WRITE_PATTERN4 0x55 | ||
69 | |||
70 | #define READ_PATTERN1 0xa500 | ||
71 | #define READ_PATTERN2 0x5a00 | ||
72 | #define READ_PATTERN3 0xaa00 | ||
73 | #define READ_PATTERN4 0x5500 | ||
74 | |||
75 | #define READ_PATTERN1_MASK 0xff00 | ||
76 | #define READ_PATTERN2_MASK 0xff00 | ||
77 | #define READ_PATTERN3_MASK 0xff00 | ||
78 | #define READ_PATTERN4_MASK 0xff00 | ||
79 | |||
80 | #define SET_REG(reg,val) reg = ((val) << 8) | ||
81 | #define SET_16BITREG(reg,val) reg = (val) | ||
82 | |||
83 | #elif CONFIG_CPU == SH7034 | ||
84 | 40 | ||
85 | /* asm optimised read & write loops */ | 41 | /* asm optimised read & write loops */ |
86 | 42 | ||